Lab 1: Cache Memory
Table of Contents
Objective
The purpose of this lab is to understand the functionality
of cache memories and to get an insight into various
trade-offs related to the design of systems with cache memories.
Time Allocation
Four hours (two lab sessions) are allocated for this lab.
Theoretical Background
You should review one of the folowing resources before
you start working on this lab:
Also, before you start working on the 2nd and 3rd problems for this lab,
you should read the instructions on how you can access the
SimpleScalar tool set on IDA machines.
Assignments
-
Cache Basics
Solve the problem 4.8 from the course book (7th edition).
If you have older versions of the book, then this is the same as problem 4.7 from 6th edition,
and problem 4.13 in the 5th edition. If you don't have the book, you can
ask for one copy of the text problem from the lab assistants or you can
take it from /home/TDTS55/docs/lab_problems.txt.
-
Locality of data
This assignment requires you to use sim-cache
for the simulation of two different architectures. You will
run two tests on each of these architectures. After you
install and run the set of examples, complete the following steps:
- Look into the configuration files used for these
experiments (
cache1.cfg and
cache2.cfg) and compare the architectures
on which the tests were run.
- Analyze the C source of the
test1.c
and test2.c programs so that you
understand how the data is being accessed. Identify
the spatial and temporal locality of data in the code.
Are the two programs functionally equivalent?
- Extract the miss rates from the output files.
Explain the differences in hit/miss rates in each case.
Based on these results, can you think of a relation between
cache associativity and locality of data?
The source code for this problem is available here.
-
Evaluation of cache configurations
This assignment requires you to use sim-cheetah in order to evaluate the performance of several cache configurations.
- Create a configuration file for
sim-cheetah
so that the simulator run will cover the following cache configurations:
all caches with a number of sets between 128 and 4096,
with a level of associativity between 1 and 8,
with a line size of 32 bytes and a LRU replacement policy.
Using the go.ss benchmark,
run the simulation for the three cases in which the cache stores
either only data, or only intructions or both (unified cache).
Example for runnning go.ss on SimpleScalar:
sim-cheetah -config config-file /home/TDTS55/spec95-big/go.ss 3 7
(go.ss is a simple program that makes the computer run go against itself.
The first parameter (e.g. 3) indicates the level of the player while
the second (e.g. 7) sets the go table size).
- For each of the three simulator runs, extract the results from the
output file and create a plot graph which shows how the miss rate
depends on the associativity. (you should use
gnuplot for plotting, or any other tool you are familiar with)
- What is the relation between the miss ratio and: the associativity, number of sets, cache size?
- Compare the overall performance of the data, instruction, and unified caches.
- In your opinion, why are such cache evaluations necessary for a designer? Give a numeric example based on the results obtained from the simulation.
What to hand-in
Return the answers for each of the previous problems.
You should use figures where you think it's necessary.
Hand-in all the configuration files used and the outputs in the required format.
Typed hand-ins are preferred rather than hand-written ones.
Resources
- Help on running the examples.
- Course notes on Cache memories
- The SimpleScalar Tool Set, Version 2.0, D. Burger, T. M. Austin.
[pdf]
- A User's and Hacker's Guide To SimpleScalar Architectural Tool Set, Todd M. Austin, 1997
[pdf]
- Stallings, William:
Computer Organization and Architecture,
6th edition, Prentice Hall International, 2003
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