@techreport{R-91-36,
PSURL = {/publications/cgi-bin/tr-fetch.pl?r-91-36+ps},
ABSTRACTURL = {/publications/cgi-bin/tr-fetch.pl?r-91-36+abstr},
ABSTRACT = {This paper describes an approach for defining a model for the VHDL descriptions which can 
be used for test generation purpose. The VHDL description can be transformed to this model 
by semantic preserving transformations without lost of information needed for test generation 
purpose. Together with the model definition a unified fault model is defined which can be 
easily related to well known fault models defined on different levels of hardware abstraction 
(such as stack-at-0/1, wrong function selection and controller state selection fault). Finally, a 
discussion about possible test generation procedures based on the model is included.
},
TITLE = {Toward Automatic Tets Pattern Generation for VHDL Description},
AUTHOR = {Krzysztof Kuchcinski},
EMAIL = {krzku@ida.liu.se},
YEAR = {1991},
NUMBER = {R-91-36},
INSTITUTION = ida,
ADDRESS = idaaddr,
IDANR = {LiTH-IDA-R-91-36},
NOTE = {Also in Proceedings of the EURO-VHDL 91, Sweden, Stockholm, September 8-11, 1991}