Title: The future of Semiconductors Moore or less? DATE: Wednesday, September 8 TIME: 10:15 to 11:30 ROOM: VISIONEN (in B-huset, ISY) Abstract: Over the past four decades, semiconductor technologies have made tremendous progress in density, functionality and performance. According to the International Technology Roadmap for Semiconductors (ITRS), this growth is expected to continue far into the next decade. However, several icebergs are appearing on the horizon and we are not sure whether we can manage the semiconductor ship to navigate safely around them. The presentation gives an overview of the current status of CMOS technologies and design parameters and also presents the characteristics of a chip by the year 2014 according to the ITRS roadmap. However, the focus will be on the roadblocks that lie ahead of us and which may and will limit the future pace of scaling **************** Speaker Biography Harry Veendrick graduated from the Technical University Eindhoven, the Netherlands, in 1977. In the same year he joined Philips Research Laboratories, also in Eindhoven, where he has been involved in the design of memories, gate arrays and complex video-signal processors. He holds 14 patents in the area of CMOS circuit design, with another ten patents pending, and he is the (co-)author of several publications on robust, high-performance and low-power CMOS IC design. In this respect, he has contributed to many conferences and conference workshops, as reviewer, speaker, invited speaker, panellist, organizer, guest editor and program committee member. In addition, he is the author of MOS ICs (VCH 1992), Deep-Submicron CMOS ICs, from Basics to Asics (Kluwer: 1-st edition 2000, 2-nd edition 2002) and he has been actively involved in the training of more than 3000 semiconductor design, test, product and process engineers. He is a co-author of Low-Power Electronics Design (CRC Press, 2004) His principle research interests include the design of low-power and high-speed complex digital CMOS circuits, with an emphasis on deep-submicron physical effects and scaling aspects. Currently he leads the Deep-Submicron Electrical Design Cluster within the research group Digital Design and Test at Philips Research Labs. Complementary to this is his expertise related to IC technology, which allows him to act as an interface between digital IC design and IC process technology. In 2002 he received the PhD degree in electronic engineering from the Technical University of Eindhoven, The Netherlands. He is a Research Fellow at Philips Research Laboratories and a Visiting Professor to the Department of Electronic and Electrical Engineering of the University of Strathclyde, Glasgow, Scotland, UK.