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Modeling and Verification of Embedded Systems

Project Description

The focus of this project is the development of a high-level representation and formal verification techniques suitable for real-time embedded systems.

The main objectives of the project are:

  • Developing a modeling formalism that captures the most relevant aspects of embedded systems and, at the same time, has formal semantics.
  • Devising formal verification techniques applicable to systems represented in our model.

Project Members

Selected Publications