Preemptive Power Constrained TAM Scheduling for Scan-based System-on-Chip
Nara Institute of Science and Technology (NAIST), ISSN 0919-9527, NAIST-IS-TR2002003, Japan, January 2002.
ABSTRACT
[LF02] Erik Larsson, Hideo Fujiwara, "Preemptive Power Constrained TAM Scheduling for Scan-based System-on-Chip", Nara Institute of Science and Technology (NAIST), ISSN 0919-9527, NAIST-IS-TR2002003, Japan, January 2002. |
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