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jaytu_vlsi09

Capture Power Reduction for Modular System-on-Chip Test

Jaynarayan T Tudu
 
Erik Larsson
Virendra Singh
 
Adit Singh

IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009.

ABSTRACT


[TLSS09] Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Adit Singh, "Capture Power Reduction for Modular System-on-Chip Test", IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009.
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)