A Heuristic for Wiring-Aware Built-In Self-Test Synthesis
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools, Rennes, France, August 31-September 3, 2004, pp. 408 - 415
ABSTRACT
This paper addresses the problem of BIST synthesis that takes into account wiring area. A technique for minimizing BIST hardware overhead is presented. The technique uses results of symbolic testability analysis to guarantee testability of all modules in the design. New behavioral-level BIST enhancement metrics are used to guide synthesis in such a way that the number of testability enhancements is minimized. The technique is not only fast but also adds low BIST overhead.
[RPE04] Abdil Rashid Mohamed, Zebo Peng, Petru Eles, "A Heuristic for Wiring-Aware Built-In Self-Test Synthesis", EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, Architectures, Methods and Tools, Rennes, France, August 31-September 3, 2004, pp. 408 - 415 |
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