Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012.
ABSTRACT
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.
[SIL12] Breeta SenGupta, Urban Ingelsson, Erik Larsson, "Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias", 25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012. |
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