Test Planning for Core-based 3D Stacked ICs under Power Constraints
3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012.
ABSTRACT
Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D SICs with two chips and 3D SICs with an arbitrary number of chips. We motivate the problem by demostrating the trade-off between test time and hardware, within a power constraint, while arriving at the minimal cost.
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[SIL12] Breeta SenGupta, Urban Ingelsson, Erik Larsson, "Test Planning for Core-based 3D Stacked ICs under Power Constraints", 3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012. |
