BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints
International Test Synthesis Workshop, Santa Barbara, USA, March 26-28, 2001
ABSTRACT
This paper describes an approach to optimize BIST resource usage for system on chip under testing time constraints. A symbolic testability analysis technique is used to analyze testability of the design for pseudorandom BIST. The testability analysis results are used to guide high-level synthesis of system on chip blocks with BIST mechanisms. Finally, BIST resources are optimized to comply with test time constraints. Key words: BIST, testing time, symbolic testability analysis, and high-level BIST synthesis.
[RPE01] Abdil Rashid Mohamed, Zebo Peng, Petru Eles, "BIST Synthesis: An Approach to Resource Optimization under Test Time Constraints", International Test Synthesis Workshop, Santa Barbara, USA, March 26-28, 2001 |
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