A Formal Verification Approach for IP-based Designs
Forum on Specification and Design Languages, Lille, France, September 13-17, 2004, pp. 556-567
ABSTRACT
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already verified by their designers and which are considered correct under the assumption that the environment satisfies certain properties assumed by the component. What remains to be verified is the glue logic inserted between the components. Each such glue logic is verified one at a time using model checking techniques. A big difficulty with such an approach is the question how to handle the connected components and the rest of the system in the verification of the glue logic, which only constitutes a small part of the design. In this paper, algorithms for generating a model corresponding to the rest of the system are discussed together with guidelines on how and when to use them. The methodology is illustrated by a small case study on a mobile telephone.
[KEP04] Daniel Karlsson, Petru Eles, Zebo Peng, "A Formal Verification Approach for IP-based Designs", Forum on Specification and Design Languages, Lille, France, September 13-17, 2004, pp. 556-567 |
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