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AUTHOR:TATJANA SHCHENOVA
Found 2 entries
  1. Hybrid BIST Energy Minimisation Technique for System-on-Chip Testing
    Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng
    IEE Proceedings - Computers and Digital Techniques, Vol. 153 , Issue 4, July 2006, pp. 208-216

  2. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment
    Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng
    10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7

( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)