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AUTHOR:JAYNARAYAN T TUDU
Found 2 entries
  1. Capture Power Reduction for Modular System-on-Chip Test
    Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Adit Singh
    IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009.

  2. On Minimization of Peak Power for Scan Circuit during Test
    Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Vishwani Agrawal
    European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009, pp. 25-30.

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