Abstract - Ph D thesis Alexandru Andrei

Energy Efficient and Predictable Design of Real-Time Embedded Systems


This thesis addresses several issues related to the design and optimization of
embedded systems. In particular, in the context of time-constrained embedded systems,
the thesis investigates two problems: the minimization of the
energy consumption and the implementation of predictable applications on
multiprocessor system-on-chip platforms.

Power consumption is one of the most limiting factors in electronic systems today.
Two techniques that have been shown to reduce the power consumption effectively
are dynamic voltage selection and adaptive body biasing. The reduction is achieved
by dynamically adjusting the voltage and performance settings according to the
application needs. Energy minimization is addressed using both offline and online
optimization approaches.

Offline, we solve optimally the combined supply voltage and body bias selection
problem for multiprocessor systems with imposed time constraints, explicitly taking
into account the transition overheads implied by changing voltage levels.
The voltage selection technique is applied not only to processors, but also to buses
with repeaters and fat wires. We investigate the continuous voltage selection as well as
its discrete counterpart. While the above mentioned methods minimize the active energy,
we propose an approach that combines voltage selection and processor shutdown in order
to optimize the total energy.

In order to take full advantage of slack that arises from variations in the execution time,
it is important to recalculate the voltage and performance settings during run-time,
i.e., online. However, voltage scaling is computationally expensive, and, thus, performed
at runtime, significantly hampers the possible energy savings. To overcome the online
complexity, we propose a quasi-static voltage scaling scheme, with a constant online time
complexity. This allows to increase the exploitable slack as well as to avoid the energy
dissipated due to online recalculation of the voltage settings.

Worst-case execution time (WCET) analysis and, in general, the predictability of
real-time applications implemented on multiprocessor systems has been addressed only
in very restrictive and particular contexts. One important aspect that makes the
analysis difficult is the estimation of the system's communication behavior. The traffic on
the bus does not solely originate from data transfers due to data dependencies between tasks,
but is also affected by memory transfers as result of cache misses. As opposed to the analysis
performed for a single processor system, where the cache miss penalty is constant, in a
multiprocessor system each cache miss has a variable penalty, depending on the bus
contention. This affects the tasks' WCET which, however, is needed in order to perform
system scheduling. At the same time, the WCET depends on the system schedule due to the
bus interference. In this context, we propose, an approach to worst-case execution time analysis and
system scheduling for real-time applications implemented on multiprocessor SoC architectures.

This work has been supported by CUGS--Swedish National Graduate School of Computer Science--,
SSF--Swedish Foundation for Strategic Research-via the STRINGENT program--and,
ARTIST Network of Excellence on Embedded Systems Design.



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Last modified on October 2007 by Anne Moe