Invited talks:
10.30 - 11.15 Kenneth Östberg (Carlstedt VHDL
Design), Introduction to model checking and
experiences at FMV
11.15 - 12.00 Lars-Olof Kihlström (Telelogic
AB), A practical method of using SDL
12.00 - 12.45 Arne Borälv (Prover Technology)
, Verification of Statemate specifications:
experiences and product development
Lunch
Presentations:
14.00 - 14.45 Thomas Arts (Ericsson Telecom AB),
Mads Dam, Lars-Åke Fredlund and
Dilian Gurov (SICS) A
tool for verifying telecom software
14.45 - 15.30 Simin Nadjm-Tehrani (Linköping
University), The Esprit SYRF
project, The climatic
chamber case study
15.30 - 15.45 Coffee break
15.45 - 16.30 Johan Bengtsson, Bengt Jonsson,
and Wang Yi (Uppsala University),
Verification of Timed Systems using Partial Order Reduction
Last Modified 28 Aug 98, Simin Nadjm-Tehrani