Fault-tolerant system design using active redundancy is a very challenging task that involves solving two major problems, namely finding the optimal utilization of temporal and/or spatial redundancy and the scheduling of tasks and replicas under timing constraints. When active redundancy is concerned, there is a tradeoff about whether the available resources should be spent on implementing better fault detection or realizing more redundancy. Beside software solutions, fault detection could also be implemented in hardware to reduce the time overhead, e.g. using on-chip reconfigurable FPGA fabric. Unfortunately, hardware fault detection increases the overall system cost. Hence, it is a major design decision to select which fault detector to implement for each task and where to implement them.Project Goal
The goal of this project is to solve two different optimization problems in the design of fault-tolerant systems. In order to achieve the goal, the student needs to develop optimization algorithms by extending an existing framework and using an available reliability analysis.
An one page proposal is available here [pdf]. An even more detailed project discription can be found here here [pdf].Requirements
This project will be supervised by Ke Jiang and Adrian Lifa.
Date Added: June 5th, 2012