Gert Jervan publications 1995-1998

R.Ubar, J.Raik, P.Paomets, E.Ivask, G.Jervan, A.Markus. Low-Cost CAD System for Teaching Digital Test. Proc. of the 1st European Workshop on Microelectronics Education. p. 48, Villard de Lans, France, Feb. 5-6, 1996.

R.Ubar, J.Raik, P.Paomets, E.Ivask, G.Jervan, A.Markus. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. pp. 185-188, Grenoble, France, Feb.1996.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design with Turbo Tester Software. Proc. of the 3rd Advanced Training Course: Mixed Design of Integrated Circuits and Systems MIXDES'96. pp. 589-594, Lodz, Poland, May 30 - June 1, 1996.

J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. of the 5-th Baltic Electronics Conference. pp. 237-240, Tallinn, Estonia, Oct. 1996.

R.Ubar, A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors. Proc. of the 5-th Baltic Electronics Conference. pp. 229-232, Tallinn, Estonia, Oct. 1996.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. CAD Software for Digital Test and Diagnostics. Proc. of the Conference on Design and Diagnostics of Electronic Circuits and Systems '97. Ostrava, Czech Republic, May 12-14, 1997.

M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. Proc. of the 4-th International Workshop on Computer Aided Design of Modern Devices and ICs. pp. 415-420, Poznan, Poland, June 12-14, 1997.

G.Jervan, A.Markus, J.Raik, R.Ubar. Automatic Test Generation System for VLSI. Proc. of the 1-st Electronic Circuits and Systems Conference. pp. 255-258, Bratislava, Slovakia, Sep. 4-5, 1997.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. A Set of Tools for Estimating Quality of Built-In Self-Test in Digital Circuits. Proc. of the International Symposium on Signals Circuits and Systems. pp. 362-365, Iasi, Romania, Oct. 2-3, 1997.

G.Jervan, A.Markus, J.Raik, R.Ubar. Assembling Low-Level Tests to High-Level Symbolic Test Frames. Proc. of the 15th NORCHIP Conference pp. 275-281, Tallinn, Estonia, Nov. 10-11, 1997.

M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp. 269-280.

M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems. Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. A CAD System for Teaching Digital Test. Proc. of the 2nd European Workshop on Microelectronics Education, Noordwijkerhout, the Netherlands, pp. 287-290, May 14-15, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation with Multi-Level Decision Diagram Models. Proc. of the 7-th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. DECIDER: VHDL based Test Generation System Proc. of the 5th Int. Conf. on Electronic Devices and Systems, Brno, Czech Republic, pp. 145-148, June 11-12, 1998.

G.Jervan, A.Markus, R.Ubar, J.Raik. Mixed Level Deterministic - Random Test Generation for Digital Systems. Proc. of the MIXDES'98 Conf., Lodz, Poland, pp. 335-340, June 18-20, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. DECIDER: A Decision Diagram based Hierarchical Test Generation System. Proc. of the DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. A Decision Diagram based Hierarchical Test Generator. Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct 7-9, 1998.

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