Linköping University: Students Alumni Trade and Industry/Society Internal Search

VILAB: Microelectronics Virtual Laboratory for
Cooperation in Research and Knowledge Transfer

Project Description

The main objective of the project is aimed at setting up and maintaining an East-West Virtual Laboratory (VL) fo promoting cooperative research, development and training activities among partner institutions in CEE and EC countries in the design of dependable microelectronics systems, which is one of the most dynamically developing fields of application.

The main results of the project will be: establishing of a new type of active Research Network called Virtual Laboratory and new cooperative results in design, research and teaching achieved by joint use of resources and environment of the Laboratory. As a general result of the project, a synergistic link will be created between partners active mainly in the design, and partners oriented mainly to the test research activities. This link will provide new opportunities for increasing the design quality in terms of higher dependability of the created systems and reduced time-to-market.


VILAB partners:

Industrial Advisory Board:

Related pages:

Deliverable

  • High-level Synthesis tool CAMAD

Selected Publications

  1. A Hybrid BIST Architecture and its Optimization for SoC Testing
    Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
    IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA (to be published)
  2. Using Tabu Method for Optimizing the Cost of Hybrid BIST
    Raimund Ubar, Helena Kruus, Gert Jervan, Zebo Peng
    16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), Porto, Portugal, November 20-23, 2001, pp. 445-450
  3. Fast Test Cost Calculation for Hybrid BIST in Digital Systems
    Raimund Ubar, Gert Jervan, Zebo Peng, Elmet Orasson, Rein Raidma
    Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325
  4. Test Cost Minimization for Hybrid BIST
    Gert Jervan, Zebo Peng, Raimund Ubar
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291.
  5. High-level Test Synthesis with Hierarchical Test Generation
    Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar
    IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296
  6. Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems
    Paul Pop, Petru Eles, Zebo Peng
    8th International Conference on Real-Time Computing Systems and Applications (RTCSA 2002), March 18-20, 2002, Tokyo, Japan (to be published)
  7. An Approach to Incremental Design of Distributed Embedded Systems
    Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    38th Design Automation Conference (DAC), Las Vegas, USA, June 18-22, 2001, pp. 450-455
  8. Minimizing System Modification in an Incremental Design Approach
    Paul Pop, Petru Eles, Traian Pop, Zebo Peng
    International Workshop on Hardware/Software Codesign (CODES 2001), Copenhagen, Denmark, April 25-27, 2001, pp. 183-188
  9. Scheduling with Bus Access Optimization for Distributed Embedded Systems
    Paul Pop, Petru Eles, Zebo Peng, Alex Doboli
    IEEE Transactions on VLSI Systems, vol. 8, No 5, 472-491, October 2000.
  10. Performance Estimation for Embedded Systems with Data and Control Dependencies
    Paul Pop, Petru Eles, Zebo Peng
    8th International Workshop on Hardware/Software Codesign (CODES 2000), San Diego, May 3-5, 2000, pp. 62-66
  11. Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis
    Paul Pop, Petru Eles, Zebo Peng
    Design, Automation & Test In Europe Conference (DATE 2000), Paris, France, March 27-30, 2000, pp. 567-574
  12. Schedulability Analysis for Systems with Data and Control Dependencies
    Paul Pop, Petru Eles, Zebo Peng
    12th Euromicro Conference on Real-Time Systems, Stockholm, June 19-21, 2000, pp. 201-208
  13. Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems
    Paul Pop, Petru Eles, Zebo Peng
    6th International Conference on Real-Time Computing Systems and Applications (RTCSA'99), Hong Kong, December 13-15, 1999, pages 287-294
  14. An Improved Scheduling Technique for Time-Triggered Embedded Systems
    P. Pop, P. Eles, Z. Peng
    25th Euromicro Conference, Milan, Italy, September 8-10, 1999.
  15. A Hierarchical Test Generation Technique for Embedded Systems
    G. Jervan, P. Eles, Z. Peng
    Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999
  16. An Estimation-based Technique for Test Scheduling
    E. Larsson, Z. Peng
    Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999
  17. Communication Scheduling for Time-Triggered Systems
    P. Pop, P. Eles, Z. Peng
    11th Euromicro Conference on Real-Time Systems , York, England, June 9-11, 1999 (Work in Progress Proceedings)
  18. A Behavioral-Level Testability Enhancement Technique
    E. Larsson, Z. Peng
    IEEE European Test Workshop, Constance, Germany, May 25-28, 1999
  19. A Uniform Test Generation Technique for Hardware/Software Systems
    G. Jervan, P. Eles, Z. Peng
    IEEE European Test Workshop, Constance, Germany, May 25-28, 1999
  20. Scheduling with Optimized Communication for Time-Triggered Embedded Systems
    P. Pop, P. Eles, Z. Peng
    7th International Workshop on Hardware/Software Codesign Rome, Italy, May 3-5, 1999.
  21. A Decision Diagram based Hierarchical Test Generator.
    G.Jervan, A.Markus, J.Raik, R.Ubar.
    Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct 7-9, 1998.