Dr. Maurizio Palesi, Universita' di Catania, Italy
Time: September 29, 13:15
Place: Donald Knoth
Title: "Some Key Issues in Embedded System Design"

Abstract
In this seminar we discuss some key issue in embedded system design. The
main objective of each topic is the optimization of some performance index
(eg., performance, area, power, etc). In many cases, however, it is very
important to explore the design space with the aim to optimize the design
from a multi-objective point of view. For this reason, several topics of
this seminar attack the optimization problem from a multi-objective
perspective.  The optimization of these performance indexes can be
obtained only if it is possible to evaluate the impact on them after a
design modification.

The first part of the seminar discusses issues in design of an embedded
system which runs just one specific application throughout its lifetime.
This gives designers the opportunity to develop customized architecture
for an embedded application. A hardware platform comprising of
parameterized elements (processors, memories, buses) will speed up
development of such an architecture. With a good degree of
parameterization it is possible, via specific phases in the design
methodology, to tune the parameters in such a way as to choose an optimal
platform configuration that will meet the various design constraints of an
embedded target application. The synergy achieved by using an appropriate
design methodology and a parameterized hardware platform provides the user
with a flexible design environment to explore a variety of architectural
alternatives, guaranteeing a high degree of reuse in a predictable
integration environment suitable for common driver product development
cycles.

The second part of the seminar will be devoted on some issues in on-chip
interconnection system.  A type of architecture which lays emphasis on
modularity and scalability, and is intrinsically oriented towards
supporting heterogeneous implementations is represented by Network-on-Chip
architectures. These architectures loosen the bottleneck due to delays in
signal propagation in deep-submicron technologies and provide a natural
solution to the problem of core reuse by standardising on-chip
communications. Some novel exploration dimensions such us topological
mapping, routing function and selection policies will be discussed in this
seminar.

The last part of this seminar deal with the problem of the instruction
level power modeling for the estimation of the power consumption of a
microprocessor. The STMicroelectronics ST20C2P and the ST LX VLIW
processor will be reported as a case study.