Fredag 14.15, Systemet, ISY: Analog Performance Modeling for Analog Circuit Synthesis ---------------------------------------------------------------------- Prof. Georges Gielen Katholieke Universiteit Leuven Analog circuit synthesis is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, and implies the need for hierarchical analog performance modeling. This presentation will discuss recent developments in this area, including the application of new techniques such as support vector machine modeling. Biography Georges Gielen --------------------------- Georges G.E. GIELEN received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. After serving as visiting lecturer in UC Berkeley, he joined the Department of Electrical Engineering - ESAT of the Katholieke Universiteit Leuven, where he is currently a Full Professor. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area. He has authored or coauthored four books and more than 250 papers in edited books, international journals and conference proceedings. He is a Fellow of the IEEE, and the President-Elect of the Circuits and Systems Society of IEEE.