Designing System-On-Chips at 90nm and Below: Issues and Methodology Break-Throughs

Nanometer technologies, today at 90nm and then further into 65nm and below, potentially allow System-On-Chip
of extreme performance and complexity. But they also bring dramatically increased design issues: complexity
increases at a level where system and functional verification require fundamentally new verification
techniques while implementation will have to deal with physical effects unmanageable with traditional
implementation methodology. 

In this seminar we will describe how Cadence' Unified Verification Methodology allows increased levels of
abstraction to overcome the verification crisis. On the implementation side we will introduce the silicon
virtual prototyping approach found in Cadence' Encounter Platform to solve convergence issues as well as a
path to overcome the signoff crisis.

Bio:

Peter Sandberg is technical manager for Cadence Design Systems AB in Nordic and technical account manager
for Ericsson world-wide. He has worked for Cadence for about 9 years in various positions. He brings
extensive design experience, primarily from analog-mixed signal design and digital-IC implementation, aka
place&route with verification.