Self-Test in Embedded Systems (STES)

Project Description

This is a joint project of ESLAB, the Laboratory for Dependable Computing of Chalmers University of Technology, the Electronic Design for Production Laboratory of Jönköping University, the Ericsson CadLab Research Center, FFV Test Systems and SAAB Combitech Electronics AB.

The main goal of the project is to develop efficient self-test methodologies and tools to act as an enabling technology for the design of competitive embedded systems, which will be of great importance for a wide spectrum of swedish industries. The self-test methodologies and tools will support not only production test but also other test aspects throughout the life-span of the embedded systems products, e.g. test before/under operation to cope with product safety requirements.

ESLAB is responsible for one of the sub-projects of STES, which is entitled System-Level Self-Test. We are developing a self-test strategy for system-level testing of complex embedded systems. The self-test strategy will be based on a hierarchical test architecture which makes use of both hardware and software solutions. The emphasis of the research will be on the development of a self-test strategy which can be used for those embedded systems, such as avionics control systems, which have to be tested regularly during operation and maintenance.

Our main objective is to develop a systematic system-level self test technique which utilizes the BIST functionality at the device, board, and MCM level. The technique should include both hardware and software solutions and can be used to a wide class of embedded systems. The technique will consist of a self-test architecture and its supporting design methods and tools.

Project Description and Plan (PDF)
Projektförslag (PDF)
Rapport avseende projektet STES (1999-12-27) (PDF)

Project Members

• Zebo Peng, contact person
• Gunnar Carlsson (Ericsson Cadlab Research Center)
• Petru Eles
• Erik Larsson
• Gert Jervan

Selected Publications

1. Test Cost Minimization for Hybrid BIST
   Gert Jervan, Zebo Peng and Raimund Ubar
   IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291.
2. Test Infrastructure Design and Test Scheduling Optimization
   Erik Larsson and Zebo Peng
   European Test Workshop, Cascais, Portugal, May 23-26, 2000.
3. A Technique for Test Infrastructure Design and Test Scheduling
   E. Larsson, Z. Peng
   Design and Diagnostic of Electronic Circuits and Systems Workshop (DDECS 2000), Smolenice Castle, Slovakia, April 5-7. pp. 26-29
4. System-on-Chip Test Bus Design and Test Scheduling
   E. Larsson, Z. Peng
   International Test Synthesis Workshop, Santa Barbara, USA, March 6-8.
5. High-level Test Synthesis with Hierarchical Test Generation
   G. Jervan, P. Eles, Z. Peng, J. Raik, R. Ubar
   IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296
6. An Estimation-based Technique for Test Scheduling
   E. Larsson, Z. Peng
   Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999
7. A Hierarchical Test Generation Technique for Embedded Systems
   G. Jervan, P. Eles, Z. Peng
   Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 21-24
8. A Behavioral-Level Testability Enhancement Technique
   E. Larsson, Z. Peng
   IEEE European Test Workshop, Constance, Germany, May 25-28, 1999
9. A Uniform Test Generation Technique for Hardware/Software Systems
   G. Jervan, P. Eles, Z. Peng
   IEEE European Test Workshop, Constance, Germany, May 25-28, 1999
10. Testability Analysis of Behavioral-Level VHDL Specifications
    E. Larsson, Z. Peng
    IEEE European Test Workshop , Barcelona, Spain, May 27-29, 1998.
11. High-Level Testability Analysis and Enhancement Techniques
    E. Larsson
    Licentiate Thesis No. 725, Linköpings Universitet, Linköping, Sweden, November 1998.
12. Early Prediction of Testability by Analyzing Behavioral VHDL Specifications
    E. Larsson, Z. Peng
    Norchip Conference, Tallinn, November 10-11, 1997. pp. 259-266
13. An Improved Register-Transfer Level Functional Partioning Approach for Testability
    T. Yang, Z. Peng
    Journal of Systems Architecture, 1999
14. Incremental Testability Analysis for Partial Scan Selection and Design Transformations
    T. Yang, Z. Peng
    Journal of Electronic Testing: Theory and Applications (JETTA), vol. 14, 1999, pp. 101-111, Kluwer Academic Publishers.
15. Integrated Scheduling and Allocation of High-Level Test Synthesis
    T. Yang, Z. Peng
    11th Annual IEEE International ASIC Conference (ASIC'98), Rochester, New York, Sept. 13-16, 1998, pp. 81-87.
16. Register-Transfer Level Testability Analysis and Improvement with Pseudorandom BIST
    T. Yang, Z. Peng
    IEEE International Workshop on Design, Test and Applications of Electronic Systems (WDTA-98), Dubrovnik, Croatia, June 8-10, 1998, pp. 117-120.
17. An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis
    T. Yang, Z. Peng
    Design, Automation and Test in Europe - DATE, Paris, Feb. 23-26, 1998.