Design of Heterogeneous Multiprocessor Systems
for Real-Time Applications

Project Description

This project is financed by ARTES (A network for Real-Time research and graduate Education in Sweden) and is carried out at the Embedded Systems Laboratory (ESLAB), Linköping University.

The proposed research is planned as part of an ongoing effort aimed to develop methodologies and tools for the design of real-time applications implemented as multiprocessor systems. In order to provide a cost efficient solution which at the same time satisfies the imposed performance requirements, such multiprocessor systems very often have to be heterogeneous in their structure. This means that they consist of both programmable processors and dedicated hardware components. Further heterogeneity can be identified inside each of these two domains. For example, programmable processors can be general purpose microprocessors, microcontrollers or digital signal processors (DSPs). The dedicated hardware components on the other side can be implemented as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs).

Our final goal is to develop a design environment which supports the specification, verification, analysis, and synthesis of heterogeneous multiprocessor systems for real-time applications. One of the important features of this design environment is that it starts from specifications at a high level of abstraction and supports the designer from the early phases of the design. The input specification only describes the overall functionality of the designed system and includes the imposed constraints (timing, power consumption, cost, etc). Starting from such a system specification, the design environment supports the automatic or interactive exploration of a large design space which leads to high performance and cost effective solutions. At the same time, early detection of design errors and the use of synthesis tools which take into consideration timing constraints, drastically reduces the number of functional and timing errors detected in later design phases and, thus, avoids expensive revisions of the design.

For this specific project, research efforts will concentrate in the following directions:

  • Definition of an Internal Design Representation which captures a system level view of the application and which is refined to include increasing levels of detail as the system design process evolves.
  • Development of a methodology and tools for modeling of multiprocessor architectures and processors used for embedded real-time systems; tool support for architecture selection, based on user interaction and on automatically guided design space exploration.
  • Estimation techniques and tools for performance and cost analysis at process and system level. Estimation will provide the necessary feedback to evaluate a certain design alternative and to decide on further design steps.
  • Process scheduling strategies and tools providing predictability, satisfaction of real-time constraints and low system overhead.

In co-operation with our industrial partners we target our research towards specific needs of the telecom application area. We have decided to define the basestation in a digital mobile-telephone network as a demonstrator application which will be used to validate some of the developed methodologies and tools.

The main industrial partner of this project is Ericsson Radio Systems AB. It has participated in the formulation of the research direction and the demonstrator application, in the identification of the main research issues of the project and will be involved partially in the execution of the research as well as its case studies and evaluations.

Project Members

Related publications

J. Axelsson: Analysis and Synthesis of Heterogeneous Real-time Systems, Ph.D. Dissertation, Linköping University, Sweden, 1997.

Petru Eles, Zebo Peng, Krzysztof Kuchcinski and Alexa Doboli: System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search, Journal on Design Automation for Embedded Systems, vol. 2, 5-32, 1997.

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli and Paul Pop: Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems, Proc. 24th EUROMICRO Conference, 1998.

Alexa Doboli and Petru Eles: Scheduling under Data and Control Dependencies for Heterogeneous Architectures, Proc. International Conference on Computer Design - ICCD, 1998.

Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Paul Pop and Alexa Doboli: Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems, Proc. Design, Automation and Test in Europe - DATE, 1998.

Petru Eles, Zebo Peng, Krzysztof Kuchcinski and Alexa Doboli: Hardware/Software Partitioning with Iterative Improvement Heuristics, Proc. 9th International Symposium on System Synthesis, 1996.

Last modified on Sunday September 22, 2002 by Paul Pop