The project, funded by SSF - Swedish Foundation for Strategic Research - aims at ensuring correctness of system-on-chips (SoCs) with network-on-chip (NoC) interconnect. The project is performed in the strategic mobility project. The work is performed at NXP Semiconductors, Eindhoven, Netherlands.

Motivation
Multi-processor system-on-chips (MPSOCs) consist of a number of processors combined in a single integrated circuit (IC) with supporting peripherals. It is hard to ensure that MPSOCs meet their specification due to their hardware and software complexity. Post-silicon validation is required to check that the silicon meets its specification and software test- ing/validation/verification is needed to ensure that the software meets its specification. Pre-silicon verification of software and hardware individually does not imply that the combination of software and hardware, the complete system, meets the specification because execution models may not match, and fault models may not capture all failures. As a result post- silicon debug is often required to find out why the final physical system does not work as expected.

Post-silicon debugging of MPSOCs is challenging because they contain multiple unsynchronised clock domains. Global properties about the system therefore require communica- tion between multiple distributed units in different domains (possibly far apart) with non-neglible communication delays. There are several problems to overcome. First, there is a need to be able to monitor local properties, preferably in a non-intrusive way such that the functional operation is not impacted. Second, results of local distributed monitors must be combined for global properties. Sending information over the functional interconnect may impact performance and/or cost and is therefore not desirable. Adding extensive additional infrastructure for post-silicon debug is costly. Third, there is no common time reference in the system due to the use of multiple clock domains, which complicates the notion of globally consistent view on the system. Fourth, the fact that local properties may become true millions of clock cycles apart from each other requires efficient handling and analysis of large data volumes.

In particular, we focus on:
  • possible races conditions
  • properties to be monitored at distributed units
  • flexible monitors to capture the properties
  • signalling infrastructure between monitors
  • how to program monitors to capture races

Project members

  • Erik Larsson
  • Bart Vermeulen, NXP Semiconductors
  • Kees Goossens, Eindhoven University of Technology

Publications

Publication list
Last modified on February 21, 2010 by Erik Larsson