His current research interests include test planning
for manufacturing test, test during operation
(in-situ), scan-chain diagnosis, silicon debug and
validation, IJTAG/SJTAG, stacked 3D chip test,
fault-tolerance for MPSoCs (Multi-Processor
System-on-Chip), and property checking in
distributed systems (MPSOcS with Network-on-Chip
(NoC)). He has more than 130 publications in these
areas.
Dimitar Nikolov, Mikael Väyrynen, Urban
Ingelsson, Erik Larsson, and Virendra Singh,
Optimizing Fault Tolerance for
Multi-Processor System-on-Chip,
Design
and Test Technology for Dependable
Systems-on-Chip, Raimund Ubar, Jaan Raik,
Heinrich Theodor Vierhaus (Eds.), 2010, Hardcover,
ISBN: 978-1-6096-0212-3.
Anders Larsson, Urban Ingelsson, Erik
Larsson, and Krishnendu Chakrabarty,
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs,
Design
and Test Technology for Dependable
Systems-on-Chip, Raimund Ubar, Jaan
Raik, Heinrich Theodor Vierhaus (Eds.), 2010,
Hardcover,
ISBN: 978-1-6096-0212-3.
Erik Larsson and C.P. Ravikumar,
Power-Aware System-Level DfT and Test Planning,
Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard, Nicola Nicolici, Xiaoqing Wen (Eds.), 2009, Approx. 400 p. 222 illus., Hardcover
ISBN: 978-1-4419-0927-5.
Erik Larsson and Stina Edbom,
Combined Test Data Selection and
Scheduling for Test Quality Optimization under
ATE Memory Depth Constraint, Vlsi-Soc:
From Systems To Silicon, pages 221-244,
ISBN: 978-0-387-73660-0, DOI:
10.1007/978-0-387-73661-7, October 2007.
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson,
Access Time Analysis for IEEE P1687,
IEEE Transactions on Computers, ISSN: 0018-9340
Digital Object Identifier: 10.1109/TC.2011.155
Erik Larsson and Hideo Fujiwara,
Preemptive System-on-Chip Test Scheduling,
The Institute of the Electronics, Information and Communication Engineers (IEICE)
Transactions on Information Systems - Special Issue on Test and Verification of VLSI,
March 2004, Vol.E87-D No.3 pages 620-629,
ISSN: 0916-8532,
The PDF-file at IEICE.
Xinli Gu, Jeff Rearick, Bill Eklow,
Martin Keim, Jun Qian, Artur Jutman,
Krishnendu Chakrabarty, Erik Larsson,
Re-using Chip Level DFT at Board
Level, 2012 17th IEEE European Test
Symposium (ETS), France, May 2012.
Breeta SenGupta, Urban Ingelsson and Erik Larsson,
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias Test,
25th International Conference on VLSI Design, Hyderabad,
India, January 2012.
Farrokh Ghani Zadegan, Urban Ingelsson, Golnaz
Asani, Gunnar Carlsson and Erik Larsson, Test
Scheduling in an IEEE P1687 Environment with
Resource and Power Constraints,
Asian Test Symposium (ATS 2011), Delhi,
India, November 2011.
Pramod Subramanyan, Virendra Singh, Kewal
Saluja and Erik Larsson, Adaptive
Execution Assistance for Multiplexed
Fault-Tolerant Chip Multiprocessors,
XXIX IEEE International Conference on
Computer Design (ICCD) Massachusetts, USA, October, 2011.
Dimitar Nikolov, Urban Ingelsson, Virendra
Singh and Erik Larsson, Level of
Confidence Evaluation and Its Usage for
Roll-back Recovery with Checkpointing
Optimization, 5th Workshop on
Dependable and Secure Nanocomputing
(WSDN'11) Hong Kong, June, 2011.
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar
Carlsson and Erik Larsson,
Design Automation for IEEE
P1687, Design Automation and Test in
Europe (DATE), Grenoble, France, March 2011.
Breeta SenGupta, Urban Ingelsson and Erik Larsson,
Scheduling Tests for 3D Stacked Chips
under Power Constraints,
The 6th International Symposium on Electronic
Design, Test and Applications (DELTA 2011),
Queenstown, New Zealand, January 2011.
Vinay N.S., Indira Rawat, M.S. Gaur, Erik Larsson,and Virendra Singh,
Thermal Aware Test Scheduling for Stacked
Multi-Chip-Modules, IEEE EAST-WEST DESIGN & TEST
SYMPOSIUM (EWDTS), St. Petersburg, Russia, September 17-20, 2010.
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
Test Time Analysis for IEEE P1687,
IEEE 19th Asian Test Symposium(ATS2010),
Shanghai, China, December 2010
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara,
Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach,
IEEE European Test Symposium (ETS),
Prague, Czech Republic, May 2010, pages 182-187.
Pramod Subramanyan, Virendra Singh, Kewal Saluja and Erik Larsson,
Energy-Efficient Redundant Execution for Chip MultiprocessorsGreat Lakes Symposium on VLSI on (GLSVLSI), Rhode Island, USA, May 2010.
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara,
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift PowerGreat Lakes Symposium on VLSI on (GLSVLSI), Rhode Island, USA, May 2010.
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson,
Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors,
Design Automation and Test in Europe (DATE), Dresden, Germany, March 2010.
Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson,
Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing,
IEEE International Symposium on Electronic Design, Test & Applications (DELTA), Ho Chi Minh City, Vietnam, January, 2010.
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson,
On Scan Chain Diagnosis for Intermittent Faults,
IEEE Asian Test Symposium (ATS), Taichung, Taiwan, November, 2009, pages 47-54.
Jaynarayan T Tudu, Erik Larsson, Virendra Singh, and Adit Singh,
Capture Power Reduction for Modular System-on-Chip Test,
IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July, 2009.
Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles,
What impacts course evaluation?,
12th Annual Conference on Innovation and Technology in Computer Science Education,
Dundee, Scotland, June 25-27, 2007, page 333, ISSN:0097-8418.
Erik Larsson, Julien Pouget and Zebo Peng,
Defect Probability-based System-On-Chip Test Scheduling,
6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland, April 14-16 2003.
Kim Petersen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson,
Erik Larsson, An MPSoCs demonstrator for fault injection and
fault handling in an IEEE P1687 environment, IEEE European Test
Symposium (ETS), Annecy, France, May 2012.
Breeta SenGupta, Urban Ingelsson and Erik Larsson, Test
Test Planning for Core-based 3D Stacked ICs under Power Constraints,
IEEE International Workshop on Reliability Aware System Design and Test , Hyderabad, India January 7-8, 2012.
Golnaz Asani, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson,
Test Scheduling with Constraints for IEEE P1687,
International Test Conference (ITC), Anaheim, CA, USA, September 2011.
Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson,
Study on the Level of Confidence for Roll-back Recovery with
Checkpointing, Workshop on Dependability Issues in
Deep-submicron technologies (DDT'11), Trondheim, Norway, May, 2011.
Breeta SenGupta, Urban Ingelsson and Erik Larsson,
Test Scheduling and Test Access Optimization for Core-Based
3D Stacked ICs with Through-Silicon Vias,European Test Symposium
(ETS), Trondheim, Norway, May 2011.
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik
Larsson, Automated Design for IEEE P1687,
Swedish SOC Conference (SSOCC), Varberg, Sweden, May 2-3,
2011.
Urban Ingelsson, Shih-Yen Chang and Erik Larsson, Cost reduction of wear-out monitoring by measurement point
selection,Swedish SOC Conference (SSOCC), Varberg, Sweden, May 2-3,
2011.
Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson,
Level of Confidence Study for Roll-back Recovery with Checkpointing Swedish SoC Conference (SSOCC'11),
Varberg, Sweden, May 2-3, 2011.
Breeta SenGupta, Urban Ingelsson and Erik Larsson,
Test Cost Modeling for 3D Stacked Chips with Through-Silicon
Vias, The 11th Swedish System-on-Chip Conference (SSoCC),
Varberg, Sweden, May 2011.
Breeta SenGupta, Urban Ingelsson and Erik Larsson,
Test Scheduling for 3D Stacked ICs Under Power
Constraints,
IEEE International Workshop on Realiability Aware System Design
and Test (RASDAT 2011),
Chennai, India, January 2011.
Erik Larsson, Farrokh Ghani Zadegan, Urban Ingelsson, and Gunnar Carlsson,
Test scheduling on IJTAG,
Nordic Test Forum (NTF 2010),
Drammen, Norway, November 2010.
Breeta SenGupta, Urban Ingelsson and Erik Larsson,
Power Constrained Test Scheduling for 3D Stacked Chips, First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, Texas, USA, November 2010.
Erik Larsson, Bart Vermeulen and Kees Goossens,
Checking Pipelined Distributed Global Properties for Post-silicon Debug, Workshop on RTL ATPG & DFT (WRTLT), Shanghai, China, December 2010.
Jaynarayan Tudu, Erik Larsson and Virendra Singh,
Test Scheduling of Modular System-on-Chip under Capture
Power Constraint, Workshop on RTL ATPG & DFT (WRTLT), Shanghai, China, December 2010.
Erik Larsson, Bart Vermeulen, and Kees Goossens,
Checking Pipelined Distributed and Global Properties at
Post-silicon Debug, DAC Workshop on Diagnostic Services
in Network-on-Chips (DSNoC) , Anaheim, CA, USA, June 2010.
Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Signh, and Erik Larsson,
Mapping and Scheduling of Jobs in Homogeneous NoC-based
MPSoC, The 10th Swedish System-on-Chip Conference (SSoCC),
Kolmården, Sweden, May 2010.
Breeta SenGupta, Urban Ingelsson, and Erik Larsson,
Scheduling Tests for Stacked 3D Chips under Power
Constraints, The 10th Swedish System-on-Chip Conference (SSoCC),
Kolmården, Sweden, May 2010.
Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, and Erik Larsson,
Efficient Embedding of Deterministic Test Data, The 10th Swedish System-on-Chip Conference (SSoCC),
Kolmården, Sweden, May 2010.
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik
Larsson, On-line techniques to adjust and optimize
checkpointing frequency, IEEE International Workshop on
Reliability Aware System Design and Test (RASDAT), Bangalore,
India, Jan 2010.
Jaynarayan Tudu, Virendra Singh, and Erik Larsson,
Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC,
Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November, 2009.
Venkat Rajesh, Erik Larsson, Manoj S. Gaur, and Virendra Singh,
An Even-Odd DFD Technique for Scan Chain Diagnosis,
Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November, 2009.
Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh,
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation,
7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September, 2009.
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson,
Power Efficient Redundant Execution for Chip Multiprocessors,
Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June, 2009.
Dan Adolfsson, Joanna Siew, Erik Larsson, and Erik Jan Marinissen,
Deterministic scan-chain diagnosis for intermittent faults,
European Test Symposium (ETS 2009), Sevilla, Spain, May, 2009.
Vinay N. S., Erik Larsson, and Virendra Singh,
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules,
DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 2009.
Mikael Väyrynen, Virendra Singh, and Erik Larsson,
Fault-Tolerant Average Execution Time Optimization for System-On-Chips,
Frontiers of High Performance Embedded Computing,
Bangalore, India, January 2009.
Virendra Singh and Erik Larsson,
On Reduction of Capture Power for Modular System-on-Chip Test,
IEEE Workshop on RTL and High Level Testing (WRTLT'08), Sapporo, Japan, November 2008.
Anders Larsson, Xin Zhang, Erik Larsson, and Krishnendu Chakrabarty,
SOC Test Optimization with Compression-Technique Selection,
International Test Conference, San Jose, CA, USA, October, 2008.
Michael Söderman and Erik Larsson
Test Response Compression for Diagnosis in Volume Production,
DAC'08 Workshop on Diagnostic Services in Network-on-Chips (DSNOC), Anaheim, CA, USA, June 2008.
Erik Larsson, Gunnar Carlsson, and Johan Holmqvist
Protocol Requirements in an SJTAG/IJTAG Environment,
Nordic Test Forum (NTF) Snekkersten, Denmark, November 2007.
Erik Jan Marinissen, Dan Adolfsson, Erik Larsson, Sandeep Kumar Goel,
Improved Scan Chain Diagnosis,
15th NXP IC Test Symposium (NITS'07),
Eindhoven, The Netherlands, June 11, 2007.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
Optimized Integration of Test Compression and Sharing for SOC Testing ,
Swedish System-on-Chip Conference,
Gullmarsstrand, Fiskebäckskil, May 14-15, 2007.
Johan Holmqvist, Gunnar Carlsson, Erik Larsson,
Extended STAPL as SJTAG engine,
IEEE European Test Symposium, Freiburg, Germany, May, 2007.
Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles,
What impacts course evaluation?2nd Workshop on Computer Science Education, Linköping, Sweden, April 12, 2007.
Anders Larsson, Erik Larsson, Petru
Eles, and Zebo Peng, SOC Test Scheduling with Test Set Sharing
and Broadcasting, Swedish System-on-Chip Conference
(SSoCC), Kolmården, Sweden, May 4-5, 2006.
Erik Larsson and Irtiyaz Gilani, A
Test Data Compression Architecture with Abort-on Fail Capability,
IEEE Workshop on RTL and High Level
Testing (WRTLT), Harbin, China, July 20-21, 2005.
David Bäckström, Gunnar
Carlsson and Erik Larsson, Boundary-Scan Test Control in the
ATCA Standard, IEEE European Board Test Workshop (EBTW),
Tallinn, Estonia, May 25-26, 2005.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
A Constraint Logic Programming Approach to SOC Test Scheduling,
Swedish System-on-Chip Conference(SSoCC), Tammsvik, Sweden, April 18-19, 2005.
Erik Larsson,
SOC Test Design Including Selection of Cores and Tests,
Workshop on RTL and High Level Testing (WRTLT),
Osaka, Japan, November 11-12 2004.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
A Technique for Optimization of System-on-Chip Test Data Transportation,
European Test Symposium (ETS), Corsica, France, May 23-26, 2004.
Erik Larsson,
Core Selection Integrated in the SOC TestSolution Design-Flow,
International Workshop on Test Resource Partitioning (TRP),
Napa Valley California USA, April 27 - 28 2004.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
A Technique for Optimisation of SOC Test Data Transportation,
Swedish System-on-Chip Conference (SSoCC), Båstad Sweden, April 13-14 2004.
Erik Larsson,
System-on-Chip Test Resource Partitioning and Optimization,
Swedish System-on-Chip Conference (SSoCC'03), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003.
Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, and Bruno Rouzeyre,
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling,
Swedish System-on-Chip Conference (SSOCC), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003.
Erik Larsson, Julien Pouget and Zebo Peng,
System-on-Chip Test Scheduling based on Defect Probability,
International Test Synthesis Workshop (ITSW), Santa Barbara, CA, USA, March 31-April 2, 2003.
Erik Larsson and Hideo Fujiwara,
Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers,
Workshop on RTL and High Level Testing (WRTLT), Guam, USA, November 21-22, 2002.
Erik Larsson and Hideo Fujiwara,
Preemptive TAM Scheduling of Scan-based SOC under Power Constraint ,
Fault Tolerant Computing (FTC),
Aso, Japan, January 10-12, 2002.
Erik Larsson and Zebo Peng,
System-on-Chip Test Bus Design and Test
Scheduling, Seventh International Test Synthesis
Workshop, Santa Barbara, USA, March 6-8, 2000.
Erik Larsson,
An Integrated System-Level Design for
Testability Methodology, Ph.D. thesis No. 660,
Department of Computer and Information Science,
Linköpings universitet, Sweden, December 2000.
Thesis and abstract.
The thesis is also available at Electronic press (Linköpings universitet).
Erik Larsson and Hideo Fujiwara,
Optimal Test Time for System-on-Chip
Designs using Preemptive Scheduling and
Reconfigurable Wrappers,
Nara Institute of Science and Technology
(NAIST) , NAIST-IS-TR2002011, Japan, July 2002.
Erik Larsson and Hideo Fujiwara,
Preemptive Power Constrained TAM
Scheduling for Scan-based System-on-Chip, Nara Institute of Science and Technology (NAIST) ,
ISSN 0919-9527, NAIST-IS-TR2002003, Japan, January 2002.
Gunnar Carlsson, Artur Jutman and Erik Larsson,
SoC-Level Fault Management based on P1687
IJTAG, (Tutorial), DIAMOND tutorial at DATE'11:
Handling the challenges of debugging and reliability,
Grenoble, France, March 2011.
Erik Larsson,
Testing advanced electronics systems, (Tutorial),
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Malaysia, December 2010.
Erik Larsson,
A Distributed Architecture for Checking Global
Properties during Post Silicon Debug,
(Elevator talk), International Test Conference (ITC),
Austin, Texas, USA, November 2010.
Erik Larsson,
Checking distributed properties during post silicon
debug, (Invited talk),
Tallinn Technical University, Tallinn, Estonia, February 2010.
Erik Larsson,
Throughput and Diagnosis - Co-Maximization,
(Elevator talk), International Test Conference (ITC),
Austin, Texas, USA, November 2009.
Erik Larsson,
Power-Aware SOC Test Planning, (Keynote),
Workshop on RTL and High Level Testing (WRTLT), Sapporo,
Japan, November 2008.
Erik Larsson,
Improved Scan-Chain Diagnosis, (Invited talk),
SAAB, Linköping, Sweden, May 2008.
Erik Larsson,
An X-Tolerant and Diagnostic Friendly Approach to
Integrate Abort-on-Fail Test and Test Data Compression in a
Multi-site Environment, (Invited talk),
University of Bologna, Bologna, Italy, May 2008.
Erik Larsson,
Power-Constrained Test Design for Modular
System-on-Chip, (Invited talk),
Indian Institute of Science, Bangalore, India, January 2008.
Erik Larsson,
An X-Tolerant and Diagnostic Friendly Approach to
Integrate Abort-on-Fail Test and Test Data Compression in a
Multi-site Environment, (Invited talk),
Synopsis, San Jose, CA, USA, October 2007.
Erik Larsson,
Testing System Chips, (Invited talk),
NXP Semiconductors - Corporate Innovation & Technology,
Eindhoven, The Netherlands, September 2007.
Erik Larsson,
Testing System Chips , (Invited talk),
Indian Institute of Science, Bangalore, India, August 2007.
Erik Larsson and Krishnendu Chakrabarty, (Tutorial),
Manufacturing Test Solutions for System-On-Chip
Integrated Circuits,
VLSI Design and Test Symposium (VDAT), Kolkata, India, August
2007.
Erik Larsson,
Testing System Chips , (Invited talk),
The Chinese University of Hong Kong, Hong Kong, China, January
2007.
Erik Larsson,
Testing System Chips , (Invited talk),
Nara Institute of Science and Technology, Nara, Japan, January
2007.
Erik Larsson,
Test Preparation and Application for System Chips
, (Invited talk),
Tallinn Technical University, Tallinn, Estonia, September
2006.
Erik Larsson,
Test Preparation and Application for System Chips,
, (Invited talk),
Universität Potsdam, Potsdam, Germany, May 2006.
Erik Larsson,
Design and Optimization of System-on-Chip Test
Solutions, , (Invited talk),
Philips Research, Eindhoven, The Nederlands, October 2003.
Erik Larsson,
Integrated Test Scheduling and Test Access Mechanism
Design for System-on-Chip Designs, (Invited talk),
Hitachi Central Research Laboratory, Tokyo, Japan, October 2002.
I have a number of thesis proposals. These can be performed at
Linköping University, or at Swedish companies, or at international
universities, or international companies. Please contact me directly
for further discussion.
I have supervised one Ph.D
student and a number of Master and Bachelor theses (list of students). Several students have won
prizes and the work of several students have resulted in scientific paper.
