His current research interests include test planning for manufacturing test, scan-chain diagnosis, silicon debug and validation, IJTAG/SJTAG, and optimization for fault-tolerance.
Swedish Research Council, Fault-tolerant design and optimization for multi-processor system-on-chip, 2010-2013
FP7 (ICT-2009-4) - Diagnosis and Model-Based Debug in Embedded Systems Design (DIAMOND), Small or medium-scale focused research project (STREP), 2010-2013
Erik Larsson and C.P. Ravikumar,
Power-Aware System-Level DfT and Test Planning,
Power-Aware Testing and Test Strategies for Low Power Devices, Patrick Girard, Nicola Nicolici, Xiaoqing Wen (Eds.), 2009, Approx. 400 p. 222 illus., Hardcover
ISBN: 978-1-4419-0927-5.
Erik Larsson and Stina Edbom,
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint, Vlsi-Soc: From Systems To Silicon, pages 221-244, ISBN: 978-0-387-73660-0, DOI: 10.1007/978-0-387-73661-7, October 2007.
Erik Larsson and Hideo Fujiwara,
Preemptive System-on-Chip Test Scheduling,
The Institute of the Electronics, Information and Communication Engineers (IEICE)
Transactions on Information Systems - Special Issue on Test and Verification of VLSI,
March 2004, Vol.E87-D No.3 pages 620-629,
ISSN: 0916-8532,
The PDF-file at IEICE.
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson,
Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors,
Design Automation and Test in Europe (DATE), Dresden, Germany, March 2010.
Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson,
Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing,
IEEE International Symposium on Electronic Design, Test & Applications (DELTA), Ho Chi Minh City, Vietnam, January, 2010.
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson,
On Scan Chain Diagnosis for Intermittent Faults,
IEEE Asian Test Symposium (ATS), Taichung, Taiwan, November, 2009.
Jaynarayan T Tudu, Erik Larsson, Virendra Singh, and Adit Singh,
Capture Power Reduction for Modular System-on-Chip Test,
IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July, 2009.
Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles,
What impacts course evaluation?,
12th Annual Conference on Innovation and Technology in Computer Science Education,
Dundee, Scotland, June 25-27, 2007, page 333, ISSN:0097-8418.
Erik Larsson, Julien Pouget and Zebo Peng,
Defect Probability-based System-On-Chip Test Scheduling,
6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland, April 14-16 2003.
Jaynarayan Tudu, Virendra Singh, and Erik Larsson,
Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC,
Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November, 2009.
A. Venray, Virendra Singh, and Erik Larsson,
An Even-Odd DFD Technique for Scan Chain Diagnosis,
Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November, 2009.
Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh,
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation,
7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September, 2009.
Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson,
Power Efficient Redundant Execution for Chip Multiprocessors,
Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June, 2009.
Dan Adolfsson, Joanna Siew, Erik Larsson, and Erik Jan Marinissen,
Deterministic scan-chain diagnosis for intermittent faults,
European Test Symposium (ETS 2009), Sevilla, Spain, May, 2009.
Vinay N. S., Erik Larsson, and Virendra Singh,
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules,
DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 2009.
Mikael Väyrynen, Virendra Singh, and Erik Larsson,
Fault-Tolerant Average Execution Time Optimization for System-On-Chips,
Frontiers of High Performance Embedded Computing,
Bangalore, India, January 2009.
Virendra Singh and Erik Larsson,
On Reduction of Capture Power for Modular System-on-Chip Test,
IEEE Workshop on RTL and High Level Testing (WRTLT'08), Sapporo, Japan, November 2008.
Anders Larsson, Xin Zhang, Erik Larsson, and Krishnendu Chakrabarty,
SOC Test Optimization with Compression-Technique Selection,
International Test Conference, San Jose, CA, USA, October, 2008.
Michael Söderman and Erik Larsson
Test Response Compression for Diagnosis in Volume Production,
DAC'08 Workshop on Diagnostic Services in Network-on-Chips (DSNOC), Anaheim, CA, USA, June 2008.
Erik Larsson, Gunnar Carlsson, and Johan Holmqvist
Protocol Requirements in an SJTAG/IJTAG Environment,
Nordic Test Forum (NTF) Snekkersten, Denmark, November 2007.
Erik Jan Marinissen, Dan Adolfsson, Erik Larsson, Sandeep Kumar Goel,
Improved Scan Chain Diagnosis,
15th NXP IC Test Symposium (NITS'07),
Eindhoven, The Netherlands, June 11, 2007.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
Optimized Integration of Test Compression and Sharing for SOC Testing ,
Swedish System-on-Chip Conference,
Gullmarsstrand, Fiskebäckskil, May 14-15, 2007.
Johan Holmqvist, Gunnar Carlsson, Erik Larsson,
Extended STAPL as SJTAG engine,
IEEE European Test Symposium, Freiburg, Germany, May, 2007.
Erik Larsson, Mehdi Amirijoo, Daniel Karlsson, Petru Eles,
What impacts course evaluation?2nd Workshop on Computer Science Education, Linköping, Sweden, April 12, 2007.
Anders Larsson, Erik Larsson, Petru
Eles, and Zebo Peng, SOC Test Scheduling with Test Set Sharing
and Broadcasting, Swedish System-on-Chip Conference
(SSoCC), Kolmården, Sweden, May 4-5, 2006.
Erik Larsson and Irtiyaz Gilani, A
Test Data Compression Architecture with Abort-on Fail Capability,
IEEE Workshop on RTL and High Level
Testing (WRTLT), Harbin, China, July 20-21, 2005.
David Bäckström, Gunnar
Carlsson and Erik Larsson, Boundary-Scan Test Control in the
ATCA Standard, IEEE European Board Test Workshop (EBTW),
Tallinn, Estonia, May 25-26, 2005.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
A Constraint Logic Programming Approach to SOC Test Scheduling,
Swedish System-on-Chip Conference(SSoCC), Tammsvik, Sweden, April 18-19, 2005.
Erik Larsson,
SOC Test Design Including Selection of Cores and Tests,
Workshop on RTL and High Level Testing (WRTLT),
Osaka, Japan, November 11-12 2004.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
A Technique for Optimization of System-on-Chip Test Data Transportation,
European Test Symposium (ETS), Corsica, France, May 23-26, 2004.
Erik Larsson,
Core Selection Integrated in the SOC TestSolution Design-Flow,
International Workshop on Test Resource Partitioning (TRP),
Napa Valley California USA, April 27 - 28 2004.
Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng,
A Technique for Optimisation of SOC Test Data Transportation,
Swedish System-on-Chip Conference (SSoCC), Båstad Sweden, April 13-14 2004.
Erik Larsson,
System-on-Chip Test Resource Partitioning and Optimization,
Swedish System-on-Chip Conference (SSoCC'03), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003.
Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, and Bruno Rouzeyre,
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling,
Swedish System-on-Chip Conference (SSOCC), Sunbyholms Slott, Eskilstuna, Sweden, April 8-9, 2003.
Erik Larsson, Julien Pouget and Zebo Peng,
System-on-Chip Test Scheduling based on Defect Probability,
International Test Synthesis Workshop (ITSW), Santa Barbara, CA, USA, March 31-April 2, 2003.
Erik Larsson and Hideo Fujiwara,
Optimal Test Access Mechanism Scheduling using Preemption and Reconfigurable Wrappers,
Workshop on RTL and High Level Testing (WRTLT), Guam, USA, November 21-22, 2002.
Erik Larsson and Hideo Fujiwara,
Preemptive TAM Scheduling of Scan-based SOC under Power Constraint ,
Fault Tolerant Computing (FTC),
Aso, Japan, January 10-12, 2002.
Erik Larsson and Zebo Peng,
System-on-Chip Test Bus Design and Test Scheduling, Seventh International Test Synthesis Workshop, Santa Barbara, USA, March 6-8, 2000.
Erik Larsson,
An Integrated System-Level Design for Testability Methodology, Ph.D. thesis No. 660,
Department of Computer and Information Science, Linköpings universitet, Sweden, December 2000.
Thesis and abstract.
The thesis is also available at Electronic press (Linköpings universitet).
Erik Larsson and Hideo Fujiwara,
Optimal Test Time for System-on-Chip Designs using Preemptive Scheduling and Reconfigurable Wrappers,
Nara Institute of Science and Technology (NAIST) , NAIST-IS-TR2002011, Japan, July 2002.
Erik Larsson and Hideo Fujiwara,
Preemptive Power Constrained TAM Scheduling for Scan-based System-on-Chip, Nara Institute of Science and Technology (NAIST) ,
ISSN 0919-9527, NAIST-IS-TR2002003, Japan, January 2002.
Erik Larsson,
Power-Aware SOC Test Planning, (Keynote),
Workshop on RTL and High Level Testing (WRTLT), Sapporo, Japan, November 2008.
Erik Larsson,
Improved Scan-Chain Diagnosis, (Invited talk),
SAAB, Linköping, Sweden, May 2008.
Erik Larsson,
An X-Tolerant and Diagnostic Friendly Approach to Integrate Abort-on-Fail Test and Test Data Compression in a Multi-site Environment, (Invited talk),
University of Bologna, Bologna, Italy, May 2008.
Erik Larsson,
Power-Constrained Test Design for Modular System-on-Chip, (Invited talk),
Indian Institute of Science, Bangalore, India, January 2008.
Erik Larsson,
An X-Tolerant and Diagnostic Friendly Approach to Integrate Abort-on-Fail Test and Test Data Compression in a Multi-site Environment, (Invited talk),
Synopsis, San Jose, CA, USA, October 2007.
Erik Larsson,
Testing System Chips, (Invited talk),
NXP Semiconductors - Corporate Innovation & Technology, Eindhoven, The Netherlands, September 2007.
Erik Larsson,
Testing System Chips , (Invited talk),
Indian Institute of Science, Bangalore, India, August 2007.
Erik Larsson and Krishnendu Chakrabarty, (Tutorial),
Manufacturing Test Solutions for System-On-Chip Integrated Circuits,
VLSI Design and Test Symposium (VDAT), Kolkata, India, August 2007.
Erik Larsson,
Testing System Chips , (Invited talk),
The Chinese University of Hong Kong, Hong Kong, China, January 2007.
Erik Larsson,
Testing System Chips , (Invited talk),
Nara Institute of Science and Technology, Nara, Japan,January 2007.
Erik Larsson,
Test Preparation and Application for System Chips ,(Invited talk),
Tallinn Technical University, Tallinn, Estonia, September 2006.
Erik Larsson,
Test Preparation and Application for System Chips, , (Invited talk),
Universität Potsdam, Potsdam, Germany, May 2006.
Erik Larsson,
Design and Optimization of System-on-Chip Test Solutions, , (Invited talk),
Philips Research, Eindhoven, The Nederlands, October 2003.
Erik Larsson,
Integrated Test Scheduling and Test Access Mechanism Design for System-on-Chip Designs, (Invited talk),
Hitachi Central Research Laboratory, Tokyo, Japan, October 2002.
I have a number of thesis proposals. These can be performed at Linköping University, or at Swedish companies, or at international universities, or international companies. Please contact me directly for further discussion.
I have supervised one Ph.D student and a number of Master and Bachelor theses (list of students). Several students have won prizes and the work of several students have resulted in scientific paper.
