Actually the PRAM model (and also the SB-PRAM machine) assume an even stronger consistency model, namely strict consistency, which means that consistency is maintained at every clock cycle (assuming existence of a global time axis) and a fixed, determinisitic order of memory accesses is determined by the programmer (at least for Weak, Common, Priority, and Combining Concurrent Write PRAMs). The SB-PRAM is the only strictly consistent MIMD machine in the world, achieved by central clocking, uniform memory access, and instruction-level synchronous execution.
In contrast, sequential consistency requires consistency only for the memory accesses in that it implies some linear order of all memory accesses by all processors such that the effect of a write access, once applied to the memory, becomes visible to all processors immediately. Sequential consistency thus does not need a global time axis. An imaginary global observer of a sequentially consistent system may see that pending reads could return the old value after the write was committed to the memory, but in that case the read was "overtaken" by the write and thus comes before the write in the linear order of memory accesses. Hence, sequential consistency is nondeterministic and not programmable. This, by the way, is also the consistency model adopted in the Asynchronous PRAM model.
Hence, "strict consistency" would be the more precise term here (although "sequential consistency" is not wrong - every strictly consistent parallel computation is also sequentially consistent). However, the term "strict consistency" is not widely used in the literature (probably because there is no other MIMD machine supporting it). This is why we used the more common term "sequential consistency" plus a verbose description of the stronger PRAM features in this book.
For further information on strict versus sequential consistency, see e.g. the survey of consistency models (ps slides) in a recent course.