8 \t \n || idle ADD .L1 {src1},{src2},{dest1} ADD .L2 {src1},{src2},{dest1} ADD .S1 {src1},{src2},{dest1} ADD .S2 {src1},{src2},{dest1} ADD .D1 {src1},{src2},{dest1} ADD .D2 {src1},{src2},{dest1} ADD .L1 #{src1},{src2},{dest1} ADD .L2 #{src1},{src2},{dest1} ADD .S1 #{src1},{src2},{dest1} ADD .S2 #{src1},{src2},{dest1} ADD .D1 #{src1},{src2},{dest1} ADD .D2 #{src1},{src2},{dest1} ADD .L1 {src1},#{src2},{dest1} ADD .L2 {src1},#{src2},{dest1} ADD .S1 {src1},#{src2},{dest1} ADD .S2 {src1},#{src2},{dest1} ADD .D1 {src1},#{src2},{dest1} ADD .D2 {src1},#{src2},{dest1} ADD .L1X {src1},{src2},{dest1} ADD .L2X {src1},{src2},{dest1} ADD .S1X {src1},{src2},{dest1} ADD .S2X {src1},{src2},{dest1} ADD .D1X {src1},{src2},{dest1} ADD .D2X {src1},{src2},{dest1} ADD .L1 #{src1},{src2},{dest1} ADD .L2 #{src1},{src2},{dest1} ADD .L1 #{src1},{src2},{dest1} ADD .L2 #{src1},{src2},{dest1} ADD .S1 #{src1},{src2},{dest1} ADD .S2 #{src1},{src2},{dest1} ADD .D1 #{src1},{src2},{dest1} ADD .D2 #{src1},{src2},{dest1} ADD .L1 {src1},#{src2},{dest1} ADD .L2 {src1},#{src2},{dest1} ADD .S1 {src1},#{src2},{dest1} ADD .S2 {src1},#{src2},{dest1} ADD .D1 {src1},#{src2},{dest1} ADD .D2 {src1},#{src2},{dest1} ADD .L1 {src1},{src2},{dest1} ADD .L2 {src1},{src2},{dest1} ADD .S1 {src1},{src2},{dest1} ADD .S2 {src1},{src2},{dest1} ADD .D1 {src1},{src2},{dest1} ADD .D2 {src1},{src2},{dest1} ADD .L1X {src1},{src2},{dest1} ADD .L2X {src1},{src2},{dest1} ADD .S1X {src1},{src2},{dest1} ADD .S2X {src1},{src2},{dest1} ADD .D1X {src1},{src2},{dest1} ADD .D2X {src1},{src2},{dest1} ADD .L1 {src1},{src2},{dest1} ADD .L2 {src1},{src2},{dest1} ADD .S1 {src1},{src2},{dest1} ADD .S2 {src1},{src2},{dest1} ADD .D1 {src1},{src2},{dest1} ADD .D2 {src1},{src2},{dest1} MV .L1 _{src1},#{src2} MV .L1 #{src1},_{src2} MV .L2 _{src1},#{src2} MV .L2 #{src1},_{src2} MV .L1 _{src1},{src2} MV .L2 _{src1},{src2} MV .L1 {src1},_{src2} MV .L2 {src1},_{src2} MV .L1 {src1},{src2} MV .L2 {src1},{src2} MV .S1 {src1},{src2} MV .S2 {src1},{src2} MV .D1 {src1},{src2} MV .D2 {src1},{src2} MV .L1 _{src1},#{src2} MV .L1 #{src1},_{src2} MV .L2 _{src1},#{src2} MV .L2 #{src1},_{src2} MV .L1 _{src1},{src2} MV .L2 _{src1},{src2} MV .L1 {src1},_{src2} MV .L2 {src1},_{src2} MV .L1 {src1},{src2} MV .L2 {src1},{src2} MV .S1 {src1},{src2} MV .S2 {src1},{src2} MV .D1 {src1},{src2} MV .D2 {src1},{src2} MV .L1 _{src1},#{src2} MV .L1 #{src1},_{src2} MV .L2 _{src1},#{src2} MV .L2 #{src1},_{src2} MV .L1 _{src1},{src2} MV .L2 _{src1},{src2} MV .L1 {src1},_{src2} MV .L2 {src1},_{src2} MV .L1 {src1},{src2} MV .L2 {src1},{src2} MV .S1 {src1},{src2} MV .S2 {src1},{src2} MV .D1 {src1},{src2} MV .D2 {src1},{src2} LDW .D1 *{src1},{dest1} LDW .D2 *{src1},{dest1} LDW .D1 _{src1},{dest1} LDW .D2 _{src1},{dest1} LDW .D1 *{src1},{dest1} LDW .D2 *{src1},{dest1} LDW .D1 _{src1},{dest1} LDW .D2 _{src1},{dest1} LDW .D1 *{src1},{dest1} LDW .D2 *{src1},{dest1} LDW .D1 _{src1},{dest1} LDW .D2 _{src1},{dest1} LDW .D1 *{src1},{dest1} LDW .D2 *{src1},{dest1} LDW .D1 _{src1},{dest1} LDW .D2 _{src1},{dest1} LDW .D1 *{src1},{dest1} LDW .D2 *{src1},{dest1} LDW .D1 _{src1},{dest1} LDW .D2 _{src1},{dest1} MPY .M1 {src1},{src2},{dest1} MPY .M2 {src1},{src2},{dest1} MPY .M1X {src1},{src2},{dest1} MPY .M1X {src1},{src2},{dest1} MPY .M2X {src1},{src2},{dest1} MPY .M2X {src1},{src2},{dest1} MPY .M1 {src1},#{src2},{dest1} MPY .M2 {src1},#{src2},{dest1} MPY .M1 #{src1},{src2},{dest1} MPY .M2 #{src1},{src2},{dest1} MPY .M1 {src1},#{src2},{dest1} MPY .M2 {src1},#{src2},{dest1} MPY .M1 #{src1},{src2},{dest1} MPY .M2 #{src1},{src2},{dest1} SHR .S1 {src1},{src2},{dest1} SHR .S2 {src1},{src2},{dest1} SHR .S1X {src1},{src2},{dest1} SHR .M1X {src1},{src2},{dest1} SHR .S2X {src1},{src2},{dest1} SHR .S2X {src1},{src2},{dest1} SHR .S1 {src1},#{src2},{dest1} SHR .S1 #{src1},{src2},{dest1} SHR .S2 {src1},#{src2},{dest1} SHR .S2 #{src1},{src2},{dest1} CALL {src1} SUB .L1 {src1},{src2},{dest1} SUB .L2 {src1},{src2},{dest1} SUB .S1 {src1},{src2},{dest1} SUB .S2 {src1},{src2},{dest1} SUB .D1 {src1},{src2},{dest1} SUB .D2 {src1},{src2},{dest1} SUB .L1 #{src1},{src2},{dest1} SUB .L2 #{src1},{src2},{dest1} SUB .S1 #{src1},{src2},{dest1} SUB .S2 #{src1},{src2},{dest1} SUB .D1 #{src1},{src2},{dest1} SUB .D2 #{src1},{src2},{dest1} SUB .L1 {src1},#{src2},{dest1} SUB .L2 {src1},#{src2},{dest1} SUB .S1 {src1},#{src2},{dest1} SUB .S2 {src1},#{src2},{dest1} SUB .D1 {src1},#{src2},{dest1} SUB .D2 {src1},#{src2},{dest1} SUB .L1X {src1},{src2},{dest1} SUB .L2X {src1},{src2},{dest1} SUB .S1X {src1},{src2},{dest1} SUB .S2X {src1},{src2},{dest1} SUB .D1X {src1},{src2},{dest1} SUB .D2X {src1},{src2},{dest1} SUB .L1 {src1},{src2},{dest1} SUB .L2 {src1},{src2},{dest1} SUB .S1 {src1},{src2},{dest1} SUB .S2 {src1},{src2},{dest1} SUB .D1 {src1},{src2},{dest1} SUB .D2 {src1},{src2},{dest1} SUB .L1 #{src1},{src2},{dest1} SUB .L2 #{src1},{src2},{dest1} SUB .S1 #{src1},{src2},{dest1} SUB .S2 #{src1},{src2},{dest1} SUB .D1 #{src1},{src2},{dest1} SUB .D2 #{src1},{src2},{dest1} SUB .L1 {src1},#{src2},{dest1} SUB .L2 {src1},#{src2},{dest1} SUB .S1 {src1},#{src2},{dest1} SUB .S2 {src1},#{src2},{dest1} SUB .D1 {src1},#{src2},{dest1} SUB .D2 {src1},#{src2},{dest1} SUB .L1X {src1},{src2},{dest1} SUB .L2X {src1},{src2},{dest1} SUB .S1X {src1},{src2},{dest1} SUB .S2X {src1},{src2},{dest1} SUB .D1X {src1},{src2},{dest1} SUB .D2X {src1},{src2},{dest1} !CMPEQ .L1 #{src1},{src2} !CMPEQ .L1 {src1},#{src2} !CMPEQ .L2 #{src1},{src2} !CMPEQ .L2 {src1},#{src2} SHL .S1 {src1},{src2},{dest1} SHL .S2 {src1},{src2},{dest1} SHL .S1X {src1},{src2},{dest1} SHL .M1X {src1},{src2},{dest1} SHL .S2X {src1},{src2},{dest1} SHL .S2X {src1},{src2},{dest1} SHL .S1 {src1},#{src2},{dest1} SHL .S1 #{src1},{src2},{dest1} SHL .S2 {src1},#{src2},{dest1} SHL .S2 #{src1},{src2},{dest1} CMPGT .L1 #{src1},{src2} CMPGT .L1 {src1},#{src2} CMPGT .L2 #{src1},{src2} CMPGT .L2 {src1},#{src2} CMPGT .L1 {src1},{src2} CMPGT .L2 {src1},{src2} CMPGT .L2X {src1},{src2} CMPGT .L2X {src1},{src2} CMPGT .L1X {src1},{src2} CMPGT .L1X {src1},{src2} !CMPLT .L1 #{src1},{src2} !CMPLT .L1 {src1},#{src2} !CMPLT .L2 #{src1},{src2} !CMPLT .L2 {src1},#{src2} !CMPLT .L1 {src1},{src2} !CMPLT .L2 {src1},{src2} !CMPLT .L2X {src1},{src2} !CMPLT .L2X {src1},{src2} !CMPLT .L1X {src1},{src2} !CMPLT .L1X {src1},{src2} DVI .M1 {src1},{src2},{dest1} DVI .M2 {src1},{src2},{dest1} DVI .M1X {src1},{src2},{dest1} DVI .M1X {src1},{src2},{dest1} DVI .M2X {src1},{src2},{dest1} DVI .M2X {src1},{src2},{dest1} DVI .M1 {src1},#{src2},{dest1} DVI .M2 {src1},#{src2},{dest1} DVI .M1 #{src1},{src2},{dest1} DVI .M2 #{src1},{src2},{dest1} MV .L1 _{src1},#{src2} MV .L1 #{src1},_{src2} MV .L2 _{src1},#{src2} MV .L2 #{src1},_{src2} MV .L1 _{src1},{src2} MV .L2 _{src1},{src2} MV .L1 {src1},_{src2} MV .L2 {src1},_{src2} MV .L1 {src1},{src2} MV .L2 {src1},{src2} MV .S1 {src1},{src2} MV .S2 {src1},{src2} MV .D1 {src1},{src2} MV .D2 {src1},{src2} OR .L1 {src1},{src2},{dest1} OR .L2 {src1},{src2},{dest1} OR .S1 {src1},{src2},{dest1} OR .S2 {src1},{src2},{dest1} OR .L1 #{src1},{src2},{dest1} OR .L2 #{src1},{src2},{dest1} OR .S1 #{src1},{src2},{dest1} OR .S2 #{src1},{src2},{dest1} OR .L1 {src1},#{src2},{dest1} OR .L2 {src1},#{src2},{dest1} OR .S1 {src1},#{src2},{dest1} OR .S2 {src1},#{src2},{dest1} OR .L1X {src1},{src2},{dest1} OR .L2X {src1},{src2},{dest1} OR .S1X {src1},{src2},{dest1} OR .S2X {src1},{src2},{dest1} SHR .S1 {src1},{src2},{dest1} SHR .S2 {src1},{src2},{dest1} SHR .S1X {src1},{src2},{dest1} SHR .M1X {src1},{src2},{dest1} SHR .S2X {src1},{src2},{dest1} SHR .S2X {src1},{src2},{dest1} SHR .S1 {src1},#{src2},{dest1} SHR .S1 #{src1},{src2},{dest1} SHR .S2 {src1},#{src2},{dest1} SHR .S2 #{src1},{src2},{dest1} {dest1.SYM0.X.NAME}: MV .L2X {dest1},{src1} MV .L1X {dest1},{src1}