I am pursuing my PhD at the Embedded Systems Lab, of the Department of Computer and Information Science, Linköping University (LiU), Sweden. My research is focused on 3D IC testing, under the supervision of Prof. Erik Larsson.

I completed my masters in 2009 from the Department of Physics and Meteorology, of the Indian Institute of Technology, Kharagpur, India.

Research

• 3D Stacked Integrated Circuits
• Through Silicon Via (TSV)
• Built in Self Test (BIST)
• Design for Test
• Test Scheduling
• Boundary Scan
• Power Aware

Teaching

• TDDD33 Programming (C++)
  • Course Assistant, 2010 ht1+2

• TDDI11 Embedded Software
  • Course Assistant, 2011 vt1
  • Course Assistant, 2012 vt2

Publications

• Test Planning for Core-based 3D Stacked ICs under Power Constraints, Breeta SenGupta, Urban Ingelsson and Erik Larsson, IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2011), Hyderabad, India, January 2012.

• Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias, Breeta SenGupta, Urban Ingelsson and Erik Larsson, 25th International Conference on VLSI Design, Hyderabad, India, January 2012.

• Test Planning for 3D Stacked ICs with Through-Silicon Vias, Breeta SenGupta, Urban Ingelsson and Erik Larsson, Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Anaheim, California, USA, September 2011.

• Scheduling Tests for 3D Stacked Chips under Power Constraints, Breeta SenGupta, Urban Ingelsson and Erik Larsson, Journal of Electronic Testing: Theory and Applications (JETTA), Volume 28, Number 1, 121-135, DOI: 10.1007/s10836-011-5244-5.

• Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias, Breeta SenGupta, Urban Ingelsson and Erik Larsson, European Test Symposium (ETS), Trondheim, Norway, May 2011. (Poster)

• Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias, Breeta SenGupta, Urban Ingelsson and Erik Larsson, The 11th Swedish System-on-Chip Conference (SSoCC), Varberg, Sweden, May 2011. (not reviewed, not printed)

• Test Scheduling for 3D Stacked ICs Under Power Constraints, Breeta SenGupta, Urban Ingelsson and Erik Larsson, IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2011), Chennai, India, January 2011.

• Scheduling Tests for 3D Stacked Chips under Power Constraints, Breeta SenGupta, Urban Ingelsson and Erik Larsson, The 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 2011.

• Power Constrained Test Scheduling for 3D Stacked Chips, Breeta SenGupta, Urban Ingelsson and Erik Larsson, First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, Texas, USA, November 2010. (Poster)

• Scheduling Tests for Stacked 3D Chips under Power Constraints, Breeta SenGupta, Urban Ingelsson and Erik Larsson, The 10th Swedish System-on-Chip Conference (SSoCC), Kolmården, Sweden, May 2010. (not reviewed, not printed)

Hobbies

Indian classical music, Painting, Swimming, Basketball, watching Soccer, reading lots of novels, Photography(My most recent albums).

Useful Links

• TDDI11 Embedded Software
• x86 Assembly Guide
• x86 Instruction Set