Linköping University: Students - Alumni - Trade and Industry/Society - Internal - Search

Optimization of Real-Time Applications Implemented on Power Constrained Network-on-Chip Architectures

    Project Description


    Objectives

    Recent developments in electronic technology make it possible to produce Systems on Chip (SoC) consisting of a large number (tens, in the future hundreds) of processing elements. The interconnection structure supporting such an architecture will be closer to a sophisticated network than to current bus-based solutions. Communication strategies similar to those currently used for large networks will be applied at the chip level. Such networks on chip can be efficiently used only if the architecture platform is customized to meet the computation and communication particularities of a certain family of applications. Further, when implementing a particular application, the problem is how to map this functionality on the existing platform such that constraints regarding cost, performance, and power consumption are satisfied. System level design tools for efficient implementation of network-on-chip applications have to be based on accurate delay and power models for the processor cores, memory elements and communication infrastructure. The development of models that capture the deep submicron effects on the communication medium is a very important and challenging task. Using such a model to design a good interconnect structure is particularly interesting, in the context in which communication aspects are becoming more and more dominant with current and future technologies. Accurate power models have to be incorporated in system level routing, scheduling and mapping strategies in order to achieve power efficient implementations which provide the required quality of service. We plan to find the appropriate network structure, given a particular set of applications. An important aspect is the efficient mapping of a given set of tasks to an existing network-on-chip platform. The main problem here is to take into consideration the communication particularities of the application and to develop an application specific routing strategy which guarantees a certain level of service in the presence of dynamic load. The problems highlighted above are becoming particularly interesting in the context in which power consumption has to be kept at a minimum level. We assume that chips will run at variable, adjustable voltage levels, (which is the case with some existing chips already) and that different voltages can be simultaneously used to run parts of the network on chip platform. Further, we will show that communication speed can be dynamically varied, opening the door for optimization. In this context we plan to develop algorithms and tools for mapping and scheduling of communications and computations and for dynamic voltage scaling in the context of performance and power constraints.

    Expected Outcome

    We will develop algorithms for optimization of real-time applications, implemented on power constrained network-on-chip architectures.

    Project Members

    Selected Publications

Last modified on Sunday October 26, 2003 by Alexandru Andrei