TDTS51: Advanced Computer Architecture
The course has changed its name to TDTS55
due to the introduction of labs.
responsible and examiner: Paul Pop
secretary: Gunilla Mellheden
- 2000-12-04: Reorganized the reading instructions.
- 2000-12-04: Added more examples of exam questions (exam-questions.pdf). I will try to add some example answers as well.
- 2000-11-30: Added examples of exam questions (exam.pdf).
- 2000-11-27: All the lectures are now available on this page.
- 2000-11-23: Added links to docs about the Crusoe processor under "Course literature". Added lecture notes for lecture 10 and part of lecture 11.
- 2000-11-20: Reorganized the lectures to reflect the course plan.
- 2000-11-13: Added reading instructions.
- 2000-10-18: Course page created.
- 2000-10-23: Added all the lectures, see below.
- 2000-10-23: Slides for all the chapters in the book available, see also the book web page.
Outline, Basic computer architecture and organization,
Basic functions of a computer and its main components,
The von Neumann architecture, Historical perspective.
Some basic issues are recapitulated which are supposed to be known from
(2.1, 2.2, 3.1, 3.2, 3.3, 3.4, 5.1, 5.3, 5.4, 6.1, 6.2, 6.3, 6.4, 6.5, 6.6,
Chapter 9, 10.1, 10.3, 14.1, 14.2, 14.3, 15.1, 15.2)
The Memory System and its Organization:
Memory hierarchy, Organization of internal memories,
Cache memories, Memory Management.
(4.1, 4.2, 4.3, 7.3)
Organization of pipelined units, Pipeline hazards,
Reducing branch penalties, Branch prediction strategies.
(11.1, 11.2, 11.3, 11.4, 12.5)
Reduced Instruction Set Computer (RISC) Architectures:
An analysis of instruction execution for code generated from
high-level language programs, Compiling for RISC architectures,
Main characteristics of RISC architectures, RISC-CISC trade-offs.
(12.1, 12.2, 12.4, 12.8)
Instruction level parallelism and machine parallelism,
Hardware techniques for performance enhancement, Data dependencies,
Policies for parallel instruction execution,
Limitations of the superscalar approach.
Very Large Instruction Word (VLIW) Architectures:
The VLIW approach - advantages and limitations. Compiling for VLIW architectures. The Merced (Itanium) architecture.
Architectures for Parallel Computation:
Parallel programms, Performance of parallel computers, A classification of computer
architectures, Array processors, Multiprocessors, Multicomputers, Vector processors. Cache Coherence and the MESI Protocol.
(16.1, 16.2, 16.3, 16.6)
Architectures for Low Power Consumption: The Crusoe Processors
The Technology Behind Crusoe Processors.
The aim of the course is to present how modern computer systems work
and are built. Methods are discussed which have been developed in order
to improve the performance of current microprocessors and parallel
TSEA04 (Switching Theory and Logical Design),
TSEA19/20 (Computer Hardware and Architecture)
The course is organized as a set of lectures.
Instruction set, memory management and hierarchy, input/output and
buses, pipelining techniques, branch prediction, RISC architectures,
VLIW architectures and specific compiling techniques, superscalar
architectures, out of order execution, parallel architectures and
Written examination, 1.5 points (2.3 ECTS-points).
Course language is English.