TDTS30

TDTS30

System Design and Methodology:
Modeling and Design of Embedded Systems

Laboratory Sessions

The course includes 10 laboratory sessions (two hours each) and 2 lessons in which the course assistant will discuss different aspects about the lab assignments and their evaluation.

The lab assignments are to be done in groups of two students (using one computer). You must keep the same partner for all assignments.

You are expected to read and prepare the material related to the lab before going to the supervised laboratory sessions. In this way, you may take more advantage of the laboratory time. The sessions are intended for using CAD tools, asking questions, getting support from your lab assistant, and demonstrating your assignment when it is complete.

You will obtain 2 points for the labs.

Important notice: The course participants have been divided into three lab groups (A,B, and C). Please check webreg to find out which group you belong to. Further, please check the schedule to find the lab sessions corresponding to your lab group. Everyone is welcome to attend any lab session. However, in case there aren't enough computers available in the room, the persons in the lab group corresponding to the scheduled lab session will be given priority.

Lab Registration

You must choose your lab partner and sign up for the labs through a web interface. You log in using the same user name and password as you use when logging in on IDA's computer system. All lab groups will be supervised by Soheil Samii.

OBS! New lab registration deadline: 31th of January 2007.

Assignments

The laboratory is divided into three parts: SystemC modeling and simulation, Formal verification, and Design space exploration.

SystemC modeling and simulation
This lab consists of studying the basics of the system-level modeling language SystemC, and further use it to model and simulate a traffic light controller. You will follow the tutorial to learn the basics of SystemC needed to solve the exercises. You will find the lab description in the end of the tutorial. When you have finished and demonstrated your work, you will hand in a report discussing and presenting your solutions.

New make file: The problem with the "old" make file is that if you modify a header file (.h) then the object files (.o) corresponding to those source files (.cc) which include this header file will not be recompiled. Therefore the changes in the header files will not have the correct effect on the final executable. This is not a big problem, since you can simply do gmake clean followed by gmake to solve the problem. However, to avoid this inconvenience you can substitute the make file in the divider example with the new make file. Of course, you need to modify it to suit your programs in the lab assignments. Please look in the file and read the comments to understand how to make the appropriate changes.
Formal verification
In this lab you will use UPPAAL to model systems using timed automata and to verify some properties. You will solve several exercises in each section and turn in a report with your solutions to the proposed problems.

You will find all the information regarding formal verification and the lab assignments in its guide.
Design space exploration
This lab is divided in 5 assignments. You will study several issues related to certain aspects concerning the design of a software application (GSM codec) onto a multiprocessor platform. You have to turn in a report with your solutions to each of the proposed assignments.
A tutorial as well as the assignments can be found here.

The deadline for handing in the reports is 2 April 2007. Submissions after this deadline will not be considered until next year.

Lessons

The purpose of the lessons is to explain and clarify the issues related to the laboratory sessions.

Frequently asked questions (FAQ)

Here it is intended to collect answer to questions that come up frequently at the lab sessions. Please check here whenever you encounter a problem. If you don't find the answer to your question, then address it to the lab assistant.

SystemC modeling and simulation

Q: How can I get the name of an instance of a SystemC module?
A: Use the function name(). For example you may print the name of the module instance on the screen with the following statement: cout << name() << endl;

Q: I can compile my source files but I get errors (undefined symbol or similar error messages) when the object files are linked to an executable. What is wrong?
A: Most probably you have to edit the Makefile in order to include all the source files (.cc-files) that are included in the program. Make sure that all the .cc-files you want to compile and link together are listed in the variable SRCS in the file called Makefile.

Q: I change a header file (.h-file) but when I run gmake it doesn't have any effect. It just prints that my program is up to date. Why?
A: In your make file, you should, for each .cc-file, also specify the header files it includes. There is an explanation in the middle of this page. Look in the new make file for the divider example and adapt it to suit your needs.

Formal verification

We do not notice any difference in the verification time in the example "Fisher's mutex protocol" for n=2,...,6. Why?

The new UPPAAL version that we are using seems to be faster than what has been used previous years. If you try larger values of n you will notice a sudden increase in the verification time. However, trying larger values than 6 is not a mandatory part of the lab.

Design space exploration