Introduction
Outline, Basic computer architecture and organization, Basic functions of a computer and its main components, The von Neumann architecture, Historical perspective. Some basic issues are reviewed and are supposed to be known from previous courses. (Chapters 1.1, 1.2, 2.1, 2.2, 3.1, 3.2, 3.3, 3.4, 10.1, 10.2, 10.4, 11.1, 11.3, 11.5, 16.1, 16.2, 16.3)
The Memory System and its Organization
Memory hierarchy, Organization of internal memories, Cache memories, Memory Management. (Chapters 4.1, 4.2, 4.3, 4.4, 8.3)
Instruction Pipelining
Organization of pipelined units, Pipeline hazards, Reducing branch penalties, Branch prediction strategies. (Chapters 12.1, 12.2, 12.3, 12.4, 13.5)
Reduced Instruction Set Computer (RISC) Architectures
An analysis of instruction execution for code generated from high-level language programs, Compiling for RISC architectures, M ain characteristics of RISC architectures, RISC-CISC trade-offs. (Chapters 13.1, 13.2, 13.3, 13.4, 13.7, 13.8)
Superscalar Architectures
Instruction level parallelism and machine parallelism, Hardware techniques for performance enhancement, Data dependencies, Policies for parallel instruction execution, Limitations of the superscalar approach. (Chapters 14.1, 14.2)
Very Large Instruction Word (VLIW) Architectures
The VLIW approach - advantages and limitations. Compiling for VLIW architectures. The Merced (Itanium) architecture. (Chapters 21.1, 21.2, 21.3, 21.4, 21.5)
Architectures for Parallel Computation
Parallel programms, Performance of parallel computers, Classification of computer architectures, Array processors, Multiprocessors, Multicomputers, Vector processors. Cache Coherence and the MESI Protocol. Multi-core processors and multithreading (Chapters 17.1, 17.2, 17.3, 17.5, 17.6, 17.7)
Multi-core processors and GPUs
Multi-core hardware platform and organizations, Multithreading approches; Graphics processing units, General-purpose GPUs. (Chapters 17.4, 18.1, 18.2, 18.3 and the article Nvidia Tesla: A Unified Graphics and Computing Architecture)
Low Power Architecture
Architectual design for low power, The Crusoe Processors. (the article The Technology Behind Crusoe Processors)