TDTS08 Advanced computer architecture

Lectures

Lecture notes (2012)

Lecture notes will be available here before each lecture.

• Lecture 1: Basic Issues in Computer Architectures (PDF)

• Lecture 2: Memory Systems (PDF)

• Lecture 3: Instruction Pipelining (PDF)

• Lecture 4: Reduced Instruction Set Computers (RISC) (PDF)

• Lecture 5: Superscalar Processors (PDF)

• Lecture 6: VLIW Processors (PDF)

• Lecture 7: Parallel Processing (PDF)

• Lecture 8: SIMD Architectures (PDF)

• Lecture 9: MIMD Architectures (PDF)

• Lecture 10: Cache Coherence in Multiprocessor Systems (PDF)

• Lecture 11: Multi-Core Processors and GPUs (PDF)

Reading for GPUs: Nvidia Tesla: A Unified Graphics and Computing Architecture (PDF)

• Lecture 12: Low Power Architectures (PDF)

Reading for this lecture: The Technology Behind Crusoe Processors (PDF)

Lecture notes for the course book

• There are also lecture notes that come with the course book.

Reading instructions (for 9th Edition of the Course Book)

• Introduction

Outline, Basic computer architecture and organization, Basic functions of a computer and its main components, The von Neumann architecture, Historical perspective. Some basic issues are reviewed and are supposed to be known from previous courses. (Chapters 1.1, 1.2, 2.1, 2.2, 3.1, 3.2, 3.3, 3.4, 12.1, 12.2, 12.4, 13.1, 13.3, 13.5, 20.1, 20.2, 20.3)

• The Memory System and its Organization

Memory hierarchy, Organization of internal memories, Cache memories, Memory Management. (Chapters 4.1, 4.2, 4.3, 4.4, 8.3)

• Instruction Pipelining

Organization of pipelined units, Pipeline hazards, Reducing branch penalties, Branch prediction strategies. (Chapters 14.1, 14.2, 14.3, 14.4, 15.5)

• Reduced Instruction Set Computer (RISC) Architectures

An analysis of instruction execution for code generated from high-level language programs, Compiling for RISC architectures, M ain characteristics of RISC architectures, RISC-CISC trade-offs. (Chapters 15.1, 15.2, 15.3, 15.4, 15.7, 15.8)

• Superscalar Architectures

Instruction level parallelism and machine parallelism, Hardware techniques for performance enhancement, Data dependencies, Policies for parallel instruction execution, Limitations of the superscalar approach. (Chapters 16.1, 16.2)

• Very Large Instruction Word (VLIW) Architectures

The VLIW approach - advantages and limitations. Compiling for VLIW architectures. The Merced (Itanium) architecture. (PDF file availbe here)

• Architectures for Parallel Computation

Parallel programms, Performance of parallel computers, Classification of computer architectures, Array processors, Multiprocessors, Multicomputers, Vector processors. Cache Coherence and the MESI Protocol. Multi-core processors and multithreading (Chapters 17.1, 17.2, 17.3, 17.5, 17.6, 17.7)

• Multi-core processors and GPUs

Multi-core hardware platform and organizations, Multithreading approches; Graphics processing units, General-purpose GPUs. (Chapters 17.4, 18.1, 18.2, 18.3 and the article Nvidia Tesla: A Unified Graphics and Computing Architecture)

• Low Power Architecture

Architectual design for low power, The Crusoe Processors. (the article The Technology Behind Crusoe Processors)

Reading instructions (for 8th Edition of the Course Book)

• Here.

Page responsible: Zebo Peng
Last updated: 2012-12-07