TDTS08 Advanced Computer Architecture (2017)
Lecture notes (2017)Lecture notes will be available here before each lecture.
Lecture notes (PDF) from last year (2016)
Lecture notes for the course book
Here are the lecture notes that come with the course book.
Reading instructions (for 10th Edition of the Course Book)
The Memory System and its Organization
Reduced Instruction Set Computer (RISC) Architectures
Very Large Instruction Word (VLIW) Architectures
Architectures for Parallel Computation
Multi-core processors and GPUs
Low Power Architecture
Outline, Basic computer architecture and organization, Basic functions of a computer and its main components, The von Neumann architecture, Historical perspective. Some basic issues are reviewed and are supposed to be known from previous courses. (Chapters 1.1, 1.2, 1.3, 2.1, 2.2, 3.1, 3.2, 3.3, 3.4, 12.1, 12.2, 12.4, 13.1, 13.3, 13.5, 20.1, 20.2, 20.3)
Memory hierarchy, Organization of internal memories, Cache memories, Memory Management. (Chapters 4.1, 4.2, 4.3, 5.1, 8.3)
Organization of pipelined units, Pipeline hazards, Reducing branch penalties, Branch prediction strategies. (Chapters 14.1, 14.2, 14.3, 14.4, 15.5)
An analysis of instruction execution for code generated from high-level language programs, Compiling for RISC architectures, Main characteristics of RISC architectures, RISC-CISC trade-offs. (Chapters 15.1, 15.2, 15.3, 15.4, 15.7, 15.8)
Instruction level parallelism and machine parallelism, Hardware techniques for performance enhancement, Data dependencies, Policies for parallel instruction execution, Limitations of the superscalar approach. (Chapters 16.1, 16.2)
The VLIW approach - advantages and limitations. Compiling for VLIW architectures. The Merced (Itanium) architecture. (PDF file availbe here)
Parallel programms, Performance of parallel computers, Classification of computer architectures, Array processors, Multiprocessors, Multicomputers, Vector processors. Cache Coherence and the MESI Protocol. Multi-core processors and multithreading (Chapters 17.1, 17.2, 17.3, 17.5, 17.6, 17.7)
Multi-core hardware platform and organizations, Multithreading approches, Graphics processing units, and General-purpose GPUs. (Chapters 17.4, 18.1, 18.2, 18.3, 19.1, 19.2, 19.3 and the article Nvidia Tesla: A Unified Graphics and Computing Architecture)
Architectual design for low power, the Crusoe processors, and the ARM processors. (Chapter 1.6 and the article The Technology Behind Crusoe Processors)
Reading instructions for previous editionsHere are the reading instructions for the 8th and 9th editions of the Course Book.
Page responsible: Zebo Peng
Last updated: 2017-11-21