Lab Assignment 3: Superscalar Processors

Table of Contents

• Objective
• Time allocation
• Theoretical background
• Assignments
• Help
• What to report
• Resources

Objective

The purpose of this assignment is to get insight on what superscalarity means, how instructions are issued and scheduled in the pipelines, how pipeline bubbles appear.

Time Allocation

4 hours (2 lab sessions) are allocated for this lab.

Theoretical Background

You should review the folowing resources before you start working on this lab:

• Notes from the 5th course lecture
• Chapter 12.4 (on instruction pipelining) in the course book

Assignments

1. Choose a benchmark program from the /home/TDTS08/spec95-big subdirectory. Let us denote your chosen program with p. We recommend you to use go.ss.
2. Trace the execution of approximately 30 instructions of p, using sim-outorder with the initial superscalar architecture specified in this configuration file. Attention: You should choose instructions roughly in the middle of the program, in order to obtain meaningful simulations of the actual program. The initial instructions are typically only loading instructions that do not execute any meaningful algorithm and that do not use all units of the superscalar architecture.
3. Look into the trace file using the following command line, and observe which stages are underused.
   pipeview.pl <trace_file>
   where <trace_file> is the name of the trace file.
4. Perform several successive architectural modifications of the superscalar processor with the goal to reduce the complexity of the architecture while avoiding significantly decreasing the performance. For example, you should achieve to reduce the complexity of the architecture, but the number of total simulation cycles should not increase more than 5%. You are entitled to make the following architectural modifications. For each modification, retrace the same instructions and explain the trace differences, if any, and explain the rationale behind your modifications.
   • -fetch:speed (allowed range: 1-4)
   • -decode:width (allowed range: 1-16)
   • -issue:width (allowed range: 1-8)
   • -commit:width (allowed range: 1-8)
   • -ruu:size (allowed range: 1-32)
   • -res:ialu (allowed range: 1-4)
   • -res:imult (allowed range: 1-4)
   • -res:fpalu (allowed range: 1-2)
   • -res:fpmult (allowed range: 1-2)

Help

You can obtain explanations on optional switches of sim-outorder by using the following command line.

sim-outorder -h

The following resources can also help to understand more about the sim-outorder simulator.

• Section 4.4 from The SimpleScalar Tool Set
• A User's and Hacker's Guide to SimpleScalar Architectural Tool Set

The following resources can help to understand how to generate and view a trace.

• Section 5.1 from The SimpleScalar Tool Set

What to report

• Indicate the chosen program and the instructions you traced.
• A description of the modification you performed. Describe the rationale behind them. Indicate the impact of the modifications on the traces. Explain in details why the traces changed ("because I modified the architecture" is not a sufficiently good answer :).

Resources

• D. Burger, and T. M. Austin, The SimpleScalar Tool Set, Version 2.0, 1997.
• T. M. Austin, A User's and Hacker's Guide to SimpleScalar Architectural Tool Set, 1997.
• William Stallings, Computer Organization and Architecture, 9th edition.
• The initial configuration file for the superscalar architecture.
• Benchmark Descriptions.

Page responsible: Zebo Peng
Last updated: 2012-11-05