TDTS01 Computer aided design of electronics

Lectures

Lecture notes (2012)

• Lecture 1: Overview and Introduction (PDF)
• Lecture 2: VHDL. Basic Issues and Simulation Semantics (PDF)
• Lecture 3 & 4: VHDL. Signal Assignment and Resolved Signals (PDF)
• Lecture 5: VHDL. Component Configuration (PDF)
• Lecture 6: High-Level Synthesis. Part I (PDF)
• Lecture 7: High-Level Synthesis. Part II (PDF)
• Lecture 8: Optimization Heuristics for Synthesis (PDF)
• Lecture 9: Design for Testability (PDF)
• Lecture 10: SoC & ASIC Design at Ericsson (PDF)

Lecture notes (2011)

• Lecture 1: Overview and Introduction (PDF)
• Lecture 2: VHDL. Basic Issues and Simulation Semantics (PDF)
• Lecture 3 & 4: VHDL. Signal Assignment and Resolved Signals (PDF)
• Lecture 5: VHDL. Component Configuration (PDF)
• Lecture 6: High-Level Synthesis. Part I (PDF)
• Lecture 7: High-Level Synthesis. Part II (PDF)
• Lecture 8: Optimization Heuristics for Synthesis (PDF)
• Lecture 9: SoC & ASIC Design at Ericsson (PDF)
• Lecture 10: Design for Testability (PDF)
• Lecture 11: Built-In Self-Test (PDF)

About lecture notes

• Lecture notes will be available here before each lecture.