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TDTS01 Computer aided design of electronics
Lectures
- Lecture 1: Overview and Introduction (PDF)
- Lecture 2: VHDL. Basic Issues and Simulation Semantics (PDF)
- Lecture 3 & 4: VHDL. Signal Assignment and Resolved Signals (PDF)
- Lecture 5: VHDL. Component Configuration (PDF)
- Lecture 6: High-Level Synthesis. Part I (PDF)
- Lecture 1: Overview and Introduction (PDF)
- Lecture 2: VHDL. Basic Issues and Simulation Semantics (PDF)
- Lecture 3 & 4: VHDL. Signal Assignment and Resolved Signals (PDF)
- Lecture 5: VHDL. Component Configuration (PDF)
- Lecture 6: High-Level Synthesis. Part I (PDF)
- Lecture 7: High-Level Synthesis. Part II (PDF)
- Lecture 8: Optimization Heuristics for Synthesis (PDF)
- Lecture 9: Design for Testability (PDF)
- Invited Lecture: SoC & ASIC Design at Ericsson (PDF)
- Lecture 10: Built-In Self-Test (PDF)
Lecture notes 2013 (Lecture notes will be available here before each lecture)
Lecture notes 2012
Page responsible: Nima Aghaee
Last updated: 2013-01-29
