TDTS01 Computer aided design of electronics
- Please sign up for the lab through webreg.
Important dates and deadlines
- Grouping up and registering on webreg [deadline: 29-Jan]
- Assignment 1. Project specification and tool set experience [deadline: 05-Feb]
- Assignment 2. Compilable design and testbench [deadline: 19-Feb]
- Assignment 3. Synthesizable design [deadline: 01-Mar]
- Assignment 4. Manufacturing test [deadline: 06-Mar]
VHDL for designers. By S. Sjoholm and L. Lindh.
VHDL Cookbook (PDF)
General rules on laboration
- Feel free to contact the lab assistant in case you have any questions or doubts.
- Before you start with the lab, please carefully read the LABORATION RULES FOR UNDERGRADUATE COURSES.
Printed reports should be handed in together with the laboration covers located in print rooms.
Please note that NO handwritten report is accepted.
- The authors/presenters of a lab report/demonstration must be the SAME students as the registered in the sub-group in webreg. Inconsistent information leads to a failed lab report/demonstration.
- A lab sub-group consists of AT MOST TWO students.
If two registered students from DIFFERENT SUB-GROUPS would like to team up in a new sub-group,
BOTH should write to their lab assistants that they have an mutual aggreement on working together in the new sub-group.
Students in a sub-group should evenly distribute the workload.
One who does not meet the minimum requirement can be failed individually, regardless how his/her lab partner works.
Page responsible: Nima Aghaee
Last updated: 2013-02-26