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TDDC86 Compiler Optimizations and Code Generation

Lectures


Preliminary contents of lectures.
The slide material is subject to update without notice.

Time: Lecture topics: By: Reading directions:
128/8 15-17 General information. (PDF)
Multi-level intermediate Representations.
Common subexpression elimination. (PDF) 		C. Kessler
ALSU2e Ch. 8.4-5;
Muchnick Ch. 1.2-1.3, Ch. 4
231/8 13-15 Multi-level IRs (cont.)
Static analysis classification (PDF);
Control flow analysis (1) (PDF) 		C. Kessler
Recapitulate Depth-First Search!
ASU1e Ch. 10.4, ALSU2e Ch. 9.6, Muchnick Ch. 7
3 2/9 10-12 Control flow analysis (cont.)
 C. Kessler see above
4 8/9 08-10 Data flow analysis (1) (PDF) C. Kessler ASU1e Ch. 10.5-6, ALSU2e Ch. 9.2-4, Muchnick Ch. 8
5 9/9 10-12 Data flow analysis (2) C. Kessler
L1 11/9 15-17 Lesson 1 M. Eriksson -
614/9 13-15 Data dependence analysis and (high-level) loop transformations (PDF) C. Kessler ALSU2e Ch. 11
716/9 10-12 Loop transformations (cont.), loop parallelization and vectorization. C. Kessler (see above)
818/9 15-17 Instruction selection (PDF).
Instruction-level parallel architecture concepts, resource modeling with reservation tables.
Instruction scheduling. (PDF). 		C. Kessler ALSU2e Ch. 8.9; Muchnick Ch. 6, esp. 6.4
Handout-paper Sect. 4

Handout-paper Sect. 1-2
L221/9 13-15 Lesson 2 M. Eriksson -
923/9 10-12 Local and global instruction scheduling (cont.);
Software pipelining for loops (PDF).
Example modulo scheduling heuristic: HRMS (PDF). 		M. Eriksson ALSU Ch. 10, Muchnick Ch. 17
Handout-paper Sect. 7
1025/9 15-17 Instruction scheduling (cont.) C. Kessler (see above)
1128/9 13-15 Register allocation. (PDF).
Scheduling for Minimum Register Need. (PDF).
C. Kessler Handout-paper Sect. 6

1230/9 10-12 Phase ordering problems and Integrated Code Generation. (PDF).
Selected DSP / embedded code generation issues:
- Address code optimization (Offset assignment).
- Optimizing for parallel memory banks.
- Exploiting SIMD instructions.
- Energy optimizations. (PDF). 		C. Kessler Handout-paper Sect. 2+8


www.address-code-optimization.org
13 2/10 15-17 Autotuning / Iterative compilation (PDF).
Run-time parallelization, Speculative parallelization (PDF).
Short introduction to SSA (PDF). 		C. Kessler (References see slide sets.)


Muchnick Ch. 8.11
L3 5/10 13-15 Lesson 3 M. Eriksson -
SE1
SE2		 7/10 10-12
9/10 15-17		 Project presentations 1 + 2
 C. Kessler
SE312/10 13-15 Project presentations 3 (Reserve time slot) C. Kessler
SE413/10 08-10 Project presentations 4 (Reserve time slot) C. Kessler

Reading directions marked by
- ASU1e: refer to the book by Aho, Sethi, Ullman: Compilers Techniques, Principles, and Tools, first edition 1986;
- ALSU2e: refer to the book by Aho, Lam, Sethi, Ullman: Compilers Techniques, Principles, and Tools, second edition 2007;
- Muchnick: refer to the book by Muchnick: Advanced Compiler Design and Implementation, 1997;
- Handout-paper: refer to the book chapter by C. Kessler: Compiling for VLIW DSPs, draft chapter, 37 pages, 2009, handed out in paper form.


Page responsible: Christoph W Kessler
Last updated: 2009-10-01