TDDC33 Design for Test of Digital Systems

Course information

Papers

• A tutorial on built-in self-test. I. Principles, Agrawal, V.D., Kime, C.R., Saluja, K.K.
  ABSTRACT
  An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed.
  
  
• A tutorial on built-in self-test. 2. Applications, Agrawal, V.D., Kime, C.R., Saluja, K.K.
  ABSTRACT
  The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples.
  
  
• Design for testability - A survey, Williams, T.W. and Parker, K.P.
  ABSTRACT
  This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
  
  
• Resource-constrained system-on-a-chip test: a survey, Xu, Q. and Nicolici, N.
  ABSTRACT
  Manufacturing test is a key step in the implementation flow of modern integrated electronic products. It certifies the product quality, accelerates yield learning and influences the final cost of the device. With the ongoing shift towards the core-based system-on-a-chip (SOC) design paradigm, unique test challenges, such as test access and test reuse, are confronted. In addition, when addressing these new challenges, the SOC designers must consciously use the resources at hand, while keeping the testing time and volume of test data under control. Consequently, numerous test strategies and algorithms in test architecture design and optimisation, test scheduling and test resource partitioning have emerged to tackle the resource-constrained core-based SOC test. This paper presents a survey of the recent advances in this field.
  
  

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Last updated: 2011-08-26