@techreport{R-94-02,
PSURL = {/publications/cgi-bin/tr-fetch.pl?r-94-02+ps},
TITLE = {Digital System Simulation with VHDL in a High-Level Synthesis System},
AUTHOR = {Zebu Peng},
YEAR = {1994},
NUMBER = {R-94-02},
INSTITUTION = ida,
ADDRESS = idaaddr,
ABSTRACTURL = {/publications/cgi-bin/tr-fetch.pl?r-94-02+abstr},
ABSTRACT = {This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulatedtogether with the behavioral models of the primitive register-transfer level components which are also described in VHDL. The main feature of our approach is that the intermediate results (as well as the final results) of the high-level synthesis process can be simulated at any time and the simulation results can be used to guide the synthesis process.},
IDANR = {LiTH-IDA-R-94-02},
NOTE = {Published in Microprocessing and Microprogramming, the EUROMICRO Journal Vol 35, 1992}