@techreport{R-86-24, TITLE = {High-level Simulation of Systolic Architecture}, AUTHOR = {Johan Fagerstr{\"o}m and Mikael R.K. Patel }, YEAR = {1986}, NUMBER = {R-86-24}, INSTITUTION = ida, ADDRESS = idaaddr, ABSTRACTURL = {/publications/cgi-bin/tr-fetch.pl?r-86-24+abstr}, ABSTRACT = {Systolic architectures have proven to be cost-effective and high-performance solutions to a variety of problems often occurring in, for example, signal and image processing. Usually, the developing of a systolic solution to a problem is divided into three major steps: requirements definition, design and implementation. The design phase often consists of an ad hoc choice from a family of possible systolic solutions. To allow the designer to study and evaluate various trade- offs in different designs we propose to use a high-level simulation package tailored for systolic architectures. The system will be used for teaching under-graduates basic design principles as well as well-developed contemporary designs.}, IDANR = {LiTH-IDA-R-86-24}, NOTE = {Accepted for the International Workshop on Systolic Arrays, Oxford, July 2-4, 1986}