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Announcements
[31 May 2012] A masters student at RTSLAB was awarded the best thesis award from IDA - Ulf Magnusson. more ...
[27 February 2008] A masters student at RTSLAB was awarded the best thesis award from IDA - Johan Sigholm. more ...
[03 March 2004] A masters student at RTSLAB was awarded the best thesis award from IDA - Tobias Chyssler. more ...
[01 Jul 2003] For second year in a row a masters student at RTSLAB was awarded the best thesis
award from SNART - Mehdi Amirijoo. more ...
Master Thesis - Past Projects - AbstractHigh-Level Development and Formal Verification of Reconfigurable HardwareID: LiTH-IDA-Ex-02/102 This work studies development and formal verification of reconfigurable hardware using high-level languages, in particular Esterel, to evaluate the possible contributions to system safety. First, surveys of both implementation languages and formal verification techniques are given. Then, a complete development method from high-level specifications, formal verification and code generation for FPGA design is described. Case studies with real-world systems from the industry show that high-level techniques can be used with little loss of efficiency. Last, it is shown that using automatic model checking tools working directly on the implementation code, functional verification and reliability analysis can be both quick and practical. Keywords: Esterel, FPGA, Formal Verification, Safety-Critical Systems Author(s): Jerker Hammarberg Contact: Simin Nadjm-Tehrani Click here to return. |
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