Research seminar by Prof. Paulo Teixeira from IST/INESC-ID, Portugal. Time: Friday, May 20, 10:15. Place: John von Neumann, B-building, IDA Title: From Defect-level to System-level testing: Research at INESC-ID Abstract In this seminar, a perspective of the research work carried out at INESC-ID, Lisboa, Portugal in the area of quality and test of electronic systems will be presented. Three main areas are covered: DBT (Defects-Based Test), RTL Test and Dynamic Test. As high-quality production tests aims at screening out defective parts, test quality needs to deal with test effectiveness, i.e., the ability to uncover physical defects. A brief overview of INESC work in this area, namely the LOBS tool and the stratified sampling technique, will be reviewed. DBT is required for test quality assessment, but becomes prohibitive for testing complex chips. Hence, a methodology for RT-level testing has been developed - the masked-based BIST (m-BIST). This methodology, and its usefulness to derive tests that can be reused for structural testing will be discussed, together with two software tools - VeriDOS and ASCOPA. Finally, recent results on dynamic test will be presented. A methodology for using multiple clock schemes and multi-VDD test to uncover delay faults in a BIST environment and to ascertain the tolerance to VDD disturbances is under development, and will be presented.