Title of the lecture: Design of a Large Scale ASIC - an industry
perspective on tools and methodology. 

Abstract:

Swichcore has taken 2 generations of large highly integrated switching
silicon to the market. The products are standard CMOS designs which
integrate 28 Gigabit Ethernet ports of high level switching and routing
functionality.

In this lecture we try to describe the process from high level
specification to a product ready for volume shipment and make connection
to lessons learned. We will initially briefly touch on issues related to
fables vs ASIC models and ASIC vs FPGA choices, as well as some trends
in process geometries. After that the lecture will focus on design and
verification methodology and use of abstract models. We will then go
into tools used and the physical design process (e.g. use of automatic
routing, timing analysis and cross talk analysis). Finally we will try
to summarize what is left when the tape out is done and the steps to go
to volume production with quality.

Biography: 

Mats Thulin is VP of Engineering at Switchcore, a fables switching
semiconductor company. He has been with Switchcore since 1999 in various
functions.. Mats holds a holds a M.Sc. E. E from Lund Institute of
Technology, and has more than 10 years of experience in ASIC/FPGA
design. Prior to joining Switchcore he worked at Allgon with the digital
design of a baseband unit in a microwave radio link.