- Access Time Analysis for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
IEEE Transactions on Computers, Oct. 2012, Volume 61, Issue 10, pp 1459-1472.
- Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
Farrokh Ghani Zadegan, Urban Ingelsson, Golnaz Asani, Gunnar Carlsson, Erik Larsson
20th IEEE Asian Test Symposium (ATS 2011), New Delhi, India, November 21-23, 2011.
- Test Scheduling with Constraints for IEEE P1687 (poster)
Golnaz Asani, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
International Test Conference (ITC 2011), Anaheim, CA, USA, September 18-23, 2011.
- Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)
Breeta SenGupta, Urban Ingelsson, Erik Larsson
European Test Symposium (ETS 2011), Trondheim, Norway, May 23-27, 2011.
- SoC-Level Fault Management based on P1687 IJTAG
Gunnar Carlsson, Artur Jutman, Erik Larsson
Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.
- Measurement Point Selection for In-Operation Wear-Out Monitoring
Urban Ingelsson, Shih-Yen Chang, Erik Larsson
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011.
- Test Scheduling for 3D Stacked ICs under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011.
- Test scheduling on IJTAG
Erik Larsson, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson
Nordic Test Forum (NTF 2010), Drammen, Norway, November 23-24, 2010.
- Design Automation for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.
- Power Constrained Test Scheduling for 3D Stacked Chips (poster)
Breeta SenGupta, Urban Ingelsson, Erik Larsson
1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, November 4-5, 2010.
- Scheduling Tests for 3D Stacked Chips Under Power Constraints
Breeta SenGupta, Urban Ingelsson, Erik Larsson
6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011.
- Efficient Embedding of Deterministic Test Data
Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
- Test Time Analysis for IEEE P1687
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
- Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
5th IEEE Intl. Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 281-285.
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