Search Results

Author:VIRENDRA SINGH
Found 25 entries
  1. Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011.
  2. Study on the Level of Confidence for Roll-back Recovery with Checkpointing
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011), Trondheim, Norway, May 26-27, 2011.
  3. Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
    Pramod Subramanyan, Virendra Singh, Kewal Saluja, Erik Larsson
    XXIX IEEE International Conference on Computer Design (ICCD 2011), Massachusetts, USA, October 9-12, 2011.
  4. Level of Confidence Study for Roll-back Recovery with Checkpointing
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
  5. Optimizing Fault Tolerance for Multi-Processor System-on-Chip
    Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson, Virendra Singh
    Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
  6. Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
    Vinay N.S., Indira Rawat, M.S. Gaur, Erik Larsson, Virendra Singh
    IEEE East-West Design & Test Symposium (EWDTS10), St. Petersburg, Russia, September 17-20, 2010.
  7. Test Scheduling of Modular System-on-Chip under Capture Power Constraint
    Jaynarayan Tudu, Erik Larsson, Virendra Singh
    Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010.
  8. Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
    Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, Erik Larsson
    Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
  9. Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
    Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
    The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010, pp. 121-130.
  10. Energy-Efficient Redundant Execution for Chip Multiprocessors
    Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
    Great Lakes Symposium on VLSI on (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 143-146.
  11. Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach
    Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
    IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.
  12. Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
    Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
    Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010, pp. 73-78.
  13. On-line Techniques to Adjust and Optimize Checkpointing Frequency
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010, pp. 29-33.
  14. Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors
    Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
    Design Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010, pp. 1572-1577.
  15. Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    5th IEEE Intl. Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 281-285.
  16. Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
    Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
    10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), Hongkong, China, November 27-28, 2009, pp. 43-48.
  17. An Even-Odd DFD Technique for Scan Chain Diagnosis
    Venkat Rajesh, Erik Larsson, Manoj S. Gaur, Virendra Singh
    Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November 27-28, 2009.
  18. Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
    Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, Virendra Singh
    7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September 18-21, 2009, pp. 1-4.
  19. Power Efficient Redundant Execution for Chip Multiprocessors
    Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson
    Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009, Paper 9, pp. 1-6.
  20. Capture Power Reduction for Modular System-on-Chip Test
    Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Adit Singh
    IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009.
  21. On Minimization of Peak Power for Scan Circuit during Test
    Jaynarayan T Tudu, Erik Larsson, Virendra Singh, Vishwani Agrawal
    European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009, pp. 25-30.
  22. Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
    Vinay N. S., Erik Larsson, Virendra Singh
    DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 20-24, 2009.
  23. Fault-Tolerant Average Execution Time Optimization for System-On-Chips
    Mikael Väyrynen, Virendra Singh, Erik Larsson
    Frontiers of High Performance Embedded Computing, Bangalore, India, January, 2009.
  24. Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips
    Mikael Väyrynen, Virendra Singh, Erik Larsson
    Design Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009, pp. 484-489.
  25. On Reduction of Capture Power for Modular System-on-Chip Test
    Virendra Singh, Erik Larsson
    IEEE Workshop on RTL and High Level Testing (WRTLT'08), Sapporo, JAPAN, November 27-28, 2008.
( ! ) perl script by Giovanni Squillero with modifications from Gert Jervan   (v3.1, p5.2, September-2002-)
Last modified on Monday December 04, 2006 by Gert Jervan