Search Results

Author:URBAN INGELSSON
Found 37 entries
  1. Test Tool Qualification through Fault Injection
    Q. Wang, A. Wallin, Viacheslav Izosimov, Urban Ingelsson, Zebo Peng
    IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012.
  2. An MPSoCs Demonstrator for Fault Injection and Fault Handling in an IEEE P1687 Environment
    Kim Petersen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012.
  3. Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011.
  4. Study on the Level of Confidence for Roll-back Recovery with Checkpointing
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011), Trondheim, Norway, May 26-27, 2011.
  5. A Study of Instrument Reuse and Retargeting in P1687
    Farrokh Ghani Zadegan, Urban Ingelsson, Erik Larsson, Gunnar Carlsson
    IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011.
  6. Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012.
  7. Test Planning for Core-based 3D Stacked ICs under Power Constraints
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    3rd IEEE Intl. Workshop on Reliability Aware System Design and Test (RASDAT 2012), Hyderabad, India, January 7-8, 2012.
  8. Test Planning for 3D Stacked ICs with Through-Silicon Vias
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    2nd IEEE Intl. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Anaheim, CA, USA, September 22-23, 2011.
  9. Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
    Farrokh Ghani Zadegan, Urban Ingelsson, Erik Larsson, Gunnar Carlsson
    IEEE Design & Test of Computers, Apr. 2012, Volume 29, Issue 2, pp. 79-88.
  10. Access Time Analysis for IEEE P1687
    Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    IEEE Transactions on Computers, Oct. 2012, Volume 61, Issue 10, pp 1459-1472.
  11. Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
    Farrokh Ghani Zadegan, Urban Ingelsson, Golnaz Asani, Gunnar Carlsson, Erik Larsson
    20th IEEE Asian Test Symposium (ATS 2011), New Delhi, India, November 21-23, 2011.
  12. Test Scheduling with Constraints for IEEE P1687 (poster)
    Golnaz Asani, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    International Test Conference (ITC 2011), Anaheim, CA, USA, September 18-23, 2011.
  13. Scheduling Tests for 3D Stacked Chips under Power Constraints
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    Journal of Electronic Testing: Theory and Applications (JETTA), Feb. 2012, Volume 28, Issue 1, pp. 121-135.
  14. Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    European Test Symposium (ETS 2011), Trondheim, Norway, May 23-27, 2011.
  15. Automated Design for IEEE P1687
    Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
  16. Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
  17. Level of Confidence Study for Roll-back Recovery with Checkpointing
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
  18. Cost Reduction of Wear-Out Monitoring by Measurement Point Selection
    Urban Ingelsson, Shih-Yen Chang, Erik Larsson
    The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011 (not reviewed, not printed).
  19. Measurement Point Selection for In-Operation Wear-Out Monitoring
    Urban Ingelsson, Shih-Yen Chang, Erik Larsson
    14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011.
  20. Test Scheduling for 3D Stacked ICs under Power Constraints
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011.
  21. Test scheduling on IJTAG
    Erik Larsson, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson
    Nordic Test Forum (NTF 2010), Drammen, Norway, November 23-24, 2010.
  22. Design Automation for IEEE P1687
    Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.
  23. Power Constrained Test Scheduling for 3D Stacked Chips (poster)
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA, November 4-5, 2010.
  24. Scheduling Tests for 3D Stacked Chips Under Power Constraints
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    6th International Symposium on Electronic Design, Test and Applications (DELTA 2011), Queenstown, New Zealand, January 17-19, 2011.
  25. Optimizing Fault Tolerance for Multi-Processor System-on-Chip
    Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson, Virendra Singh
    Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
  26. Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
    Anders Larsson, Urban Ingelsson, Erik Larsson, Krishnendu Chakrabarty
    Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
  27. Efficient Embedding of Deterministic Test Data
    Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
  28. Test Time Analysis for IEEE P1687
    Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.
  29. Vdd-Aware Model for the Voltage on Bridged Nodes
    Urban Ingelsson
    Workshop track of the IEEE European Test Symposium (ETS 2010), Prague, Czech Republic, May 24-28, 2010
  30. Efficient Embedding of Deterministic Test Data
    Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
    Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
  31. Scheduling Tests for Stacked 3D Chips under Power Constraints
    Breeta SenGupta, Urban Ingelsson, Erik Larsson
    Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
  32. Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
    Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, Erik Larsson
    Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
  33. Vdd-Aware Bridge Defect Model
    Urban Ingelsson
    Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)
  34. Equation-Based Vdd-Aware Model for Resistive Bridge Behavior
    Urban Ingelsson
    IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010, pp. 34-39.
  35. On-line Techniques to Adjust and Optimize Checkpointing Frequency
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010, pp. 29-33.
  36. Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
    Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson
    5th IEEE Intl. Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 281-285.
  37. Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
    Urban Ingelsson, Sandeep-Kumar Goel, Erik Larsson, Erik-Jan Marinissen
    IEEE European Test Symposium (ETS'05), Tallinn, Estonia, May 22-25, 2005, pp. 8-13
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