- Optimizing Fault Tolerance for Multi-Processor System-on-Chip
Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson, Virendra Singh
Book Chapter in "Design and Test Technology for Dependable Systems-on-chip", Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, ISBN: 978-1-6096-0212-3, 2010.
- Fault-Tolerant Average Execution Time Optimization for System-On-Chips
Mikael Väyrynen, Virendra Singh, Erik Larsson
Frontiers of High Performance Embedded Computing, Bangalore, India, January, 2009.
- Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-on-Chips
Mikael Väyrynen, Virendra Singh, Erik Larsson
Design Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009, pp. 484-489.
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