viaiz_date09

Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors

Viacheslav Izosimov Author homepage
 
Ilia Polian
Paul Pop Author homepage
 
Petru Eles Author homepage
Zebo Peng Author homepage

Design Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009, pp. 682-687.

ABSTRACT
In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process reexecution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of reexecutions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.


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[IPPE09] Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru Eles, Zebo Peng, "Analysis and Optimization of Fault-Tolerant Embedded Systems with Hardened Processors", Design Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009, pp. 682-687.
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