ets04

A Technique for Optimization of System-on-Chip Test Data Transportation

Anders Larsson Author homepage
 
Erik Larsson Author homepage
Petru Eles Author homepage
 
Zebo Peng Author homepage

9th IEEE European Test Symposium, Corsica, France, May 23-26, 2004, pp. 179-180. (Informal Digest)

ABSTRACT
We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.


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[LLEP04] Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng, "A Technique for Optimization of System-on-Chip Test Data Transportation", 9th IEEE European Test Symposium, Corsica, France, May 23-26, 2004, pp. 179-180. (Informal Digest)
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