Test Cost Minimization for Hybrid BIST
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291.
This paper describes a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored deterministic test patterns. A method is proposed to find the optimal balance between pseudorandom and stored test patterns to perform core test with minimum time and memory, without losing test quality. Two accurate algorithms are proposed for finding the optimal time-moment to stop pseudorandom test generation and to apply stored patterns. To speed up the optimization procedure, a method is proposed for fast estimation of the expected cost for different possible solutions with very low computational cost. Experimental results have demonstrated the feasibility of the proposed approach for cost optimization of hybrid BIST.
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[JPU00] Gert Jervan, Zebo Peng, Raimund Ubar, "Test Cost Minimization for Hybrid BIST", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291.